TEXT 24
Fsl-sec4.txt Guest on 8th February 2021 09:25:17 AM
  1. =====================================================================
  2. SEC 4 Device Tree Binding
  3. Copyright (C) 2008-2020 Freescale Semiconductor Inc.
  4.  
  5.  CONTENTS
  6.    -Overview
  7.    -SEC 4 Node
  8.    -Job Ring Node
  9.    -Run Time Integrity Check (RTIC) Node
  10.    -Run Time Integrity Check (RTIC) Memory Node
  11.    -Secure Non-Volatile Storage (SNVS) Node
  12.    -Full Example
  13.  
  14. NOTE: the SEC 4 is also known as Freescale's Cryptographic Accelerator
  15. Accelerator and Assurance Module (CAAM).
  16.  
  17. =====================================================================
  18. Overview
  19.  
  20. DESCRIPTION
  21.  
  22. SEC 4 h/w can process requests from 2 types of sources.
  23. 1. DPAA Queue Interface (HW interface between Queue Manager & SEC 4).
  24. 2. Job Rings (HW interface between cores & SEC 4 registers).
  25.  
  26. High Speed Data Path Configuration:
  27.  
  28. HW interface between QM & SEC 4 and also BM & SEC 4, on DPAA-enabled parts
  29. such as the P4080.  The number of simultaneous dequeues the QI can make is
  30. equal to the number of Descriptor Controller (DECO) engines in a particular
  31. SEC version.  E.g., the SEC 4.0 in the P4080 has 5 DECOs and can thus
  32. dequeue from 5 subportals simultaneously.
  33.  
  34. Job Ring Data Path Configuration:
  35.  
  36. Each JR is located on a separate 4k page, they may (or may not) be made visible
  37. in the memory partition devoted to a particular core.  The P4080 has 4 JRs, so
  38. up to 4 JRs can be configured; and all 4 JRs process requests in parallel.
  39.  
  40. =====================================================================
  41. SEC 4 Node
  42.  
  43. Description
  44.  
  45.     Node defines the base address of the SEC 4 block.
  46.     This block specifies the address range of all global
  47.     configuration registers for the SEC 4 block.  It
  48.     also receives interrupts from the Run Time Integrity Check
  49.     (RTIC) function within the SEC 4 block.
  50.  
  51. PROPERTIES
  52.  
  53.    - compatible
  54.       Usage: required
  55.       Value type: <string>
  56.       Definition: Must include "fsl,sec-v4.0"
  57.  
  58.    - #address-cells
  59.        Usage: required
  60.        Value type: <u32>
  61.        Definition: A standard property.  Defines the number of cells
  62.            for representing physical addresses in child nodes.
  63.  
  64.    - #size-cells
  65.        Usage: required
  66.        Value type: <u32>
  67.        Definition: A standard property.  Defines the number of cells
  68.            for representing the size of physical addresses in
  69.            child nodes.
  70.  
  71.    - reg
  72.       Usage: required
  73.       Value type: <prop-encoded-array>
  74.       Definition: A standard property.  Specifies the physical
  75.           address and length of the SEC4 configuration registers.
  76.           registers
  77.  
  78.    - ranges
  79.        Usage: required
  80.        Value type: <prop-encoded-array>
  81.        Definition: A standard property.  Specifies the physical address
  82.            range of the SEC 4.0 register space (-SNVS not included).  A
  83.            triplet that includes the child address, parent address, &
  84.            length.
  85.  
  86.    - interrupts
  87.       Usage: required
  88.       Value type: <prop_encoded-array>
  89.       Definition:  Specifies the interrupts generated by this
  90.            device.  The value of the interrupts property
  91.            consists of one interrupt specifier. The format
  92.            of the specifier is defined by the binding document
  93.            describing the node's interrupt parent.
  94.  
  95.    - interrupt-parent
  96.       Usage: (required if interrupt property is defined)
  97.       Value type: <phandle>
  98.       Definition: A single <phandle> value that points
  99.           to the interrupt parent to which the child domain
  100.           is being mapped.
  101.  
  102.    Note: All other standard properties (see the ePAPR) are allowed
  103.    but are optional.
  104.  
  105.  
  106. EXAMPLE
  107.             compatible = "fsl,sec-v4.0";
  108.             #address-cells = <1>;
  109.             #size-cells = <1>;
  110.             reg = <0x300000 0x10000>;
  111.             ranges = <0 0x300000 0x10000>;
  112.             interrupt-parent = <&mpic>;
  113.             interrupts = <92 2>;
  114.       };
  115.  
  116. =====================================================================
  117. Job Ring (JR) Node
  118.  
  119.     Child of the crypto node defines data processing interface to SEC 4
  120.     across the peripheral bus for purposes of processing
  121.     cryptographic descriptors. The specified address
  122.     range can be made visible to one (or more) cores.
  123.     The interrupt defined for this node is controlled within
  124.     the address range of this node.
  125.  
  126.   - compatible
  127.       Usage: required
  128.       Value type: <string>
  129.       Definition: Must include "fsl,sec-v4.0-job-ring"
  130.  
  131.   - reg
  132.       Usage: required
  133.       Value type: <prop-encoded-array>
  134.       Definition: Specifies a two JR parameters:  an offset from
  135.           the parent physical address and the length the JR registers.
  136.  
  137.    - fsl,liodn
  138.        Usage: optional-but-recommended
  139.        Value type: <prop-encoded-array>
  140.        Definition:
  141.            Specifies the LIODN to be used in conjunction with
  142.            the ppid-to-liodn table that specifies the PPID to LIODN mapping.
  143.            Needed if the PAMU is used.  Value is a 12 bit value
  144.            where value is a LIODN ID for this JR. This property is
  145.            normally set by boot firmware.
  146.  
  147.    - interrupts
  148.       Usage: required
  149.       Value type: <prop_encoded-array>
  150.       Definition:  Specifies the interrupts generated by this
  151.            device.  The value of the interrupts property
  152.            consists of one interrupt specifier. The format
  153.            of the specifier is defined by the binding document
  154.            describing the node's interrupt parent.
  155.  
  156.    - interrupt-parent
  157.       Usage: (required if interrupt property is defined)
  158.       Value type: <phandle>
  159.       Definition: A single <phandle> value that points
  160.           to the interrupt parent to which the child domain
  161.           is being mapped.
  162.  
  163. EXAMPLE
  164.             compatible = "fsl,sec-v4.0-job-ring";
  165.             reg = <0x1000 0x1000>;
  166.             fsl,liodn = <0x081>;
  167.             interrupt-parent = <&mpic>;
  168.             interrupts = <88 2>;
  169.       };
  170.  
  171.  
  172. =====================================================================
  173. Run Time Integrity Check (RTIC) Node
  174.  
  175.   Child node of the crypto node.  Defines a register space that
  176.   contains up to 5 sets of addresses and their lengths (sizes) that
  177.   will be checked at run time.  After an initial hash result is
  178.   calculated, these addresses are checked by HW to monitor any
  179.   change.  If any memory is modified, a Security Violation is
  180.   triggered (see SNVS definition).
  181.  
  182.  
  183.   - compatible
  184.       Usage: required
  185.       Value type: <string>
  186.       Definition: Must include "fsl,sec-v4.0-rtic".
  187.  
  188.    - #address-cells
  189.        Usage: required
  190.        Value type: <u32>
  191.        Definition: A standard property.  Defines the number of cells
  192.            for representing physical addresses in child nodes.  Must
  193.            have a value of 1.
  194.  
  195.    - #size-cells
  196.        Usage: required
  197.        Value type: <u32>
  198.        Definition: A standard property.  Defines the number of cells
  199.            for representing the size of physical addresses in
  200.            child nodes.  Must have a value of 1.
  201.  
  202.   - reg
  203.       Usage: required
  204.       Value type: <prop-encoded-array>
  205.       Definition: A standard property.  Specifies a two parameters:
  206.           an offset from the parent physical address and the length
  207.           the SEC4 registers.
  208.  
  209.    - ranges
  210.        Usage: required
  211.        Value type: <prop-encoded-array>
  212.        Definition: A standard property.  Specifies the physical address
  213.            range of the SEC 4 register space (-SNVS not included).  A
  214.            triplet that includes the child address, parent address, &
  215.            length.
  216.  
  217. EXAMPLE
  218.             compatible = "fsl,sec-v4.0-rtic";
  219.             #address-cells = <1>;
  220.             #size-cells = <1>;
  221.             reg = <0x6000 0x100>;
  222.             ranges = <0x0 0x6100 0xe00>;
  223.       };
  224.  
  225. =====================================================================
  226. Run Time Integrity Check (RTIC) Memory Node
  227.   A child node that defines individual RTIC memory regions that are used to
  228.   perform run-time integrity check of memory areas that should not modified.
  229.   The node defines a register that contains the memory address &
  230.   length (combined) and a second register that contains the hash result
  231.   in big endian format.
  232.  
  233.   - compatible
  234.       Usage: required
  235.       Value type: <string>
  236.       Definition: Must include "fsl,sec-v4.0-rtic-memory".
  237.  
  238.   - reg
  239.       Usage: required
  240.       Value type: <prop-encoded-array>
  241.       Definition: A standard property.  Specifies two parameters:
  242.           an offset from the parent physical address and the length:
  243.  
  244.           1. The location of the RTIC memory address & length registers.
  245.           2. The location RTIC hash result.
  246.  
  247.   - fsl,rtic-region
  248.        Usage: optional-but-recommended
  249.        Value type: <prop-encoded-array>
  250.        Definition:
  251.            Specifies the HW address (36 bit address) for this region
  252.            followed by the length of the HW partition to be checked;
  253.            the address is represented as a 64 bit quantity followed
  254.            by a 32 bit length.
  255.  
  256.    - fsl,liodn
  257.        Usage: optional-but-recommended
  258.        Value type: <prop-encoded-array>
  259.        Definition:
  260.            Specifies the LIODN to be used in conjunction with
  261.            the ppid-to-liodn table that specifies the PPID to LIODN
  262.            mapping.  Needed if the PAMU is used.  Value is a 12 bit value
  263.            where value is a LIODN ID for this RTIC memory region. This
  264.            property is normally set by boot firmware.
  265.  
  266. EXAMPLE
  267.             compatible = "fsl,sec-v4.0-rtic-memory";
  268.             reg = <0x00 0x20 0x100 0x80>;
  269.             fsl,liodn   = <0x03c>;
  270.             fsl,rtic-region  = <0x12345678 0x12345678 0x12345678>;
  271.       };
  272.  
  273. =====================================================================
  274. Secure Non-Volatile Storage (SNVS) Node
  275.  
  276.     Node defines address range and the associated
  277.     interrupt for the SNVS function.  This function
  278.     monitors security state information & reports
  279.     security violations.
  280.  
  281.   - compatible
  282.       Usage: required
  283.       Value type: <string>
  284.       Definition: Must include "fsl,sec-v4.0-mon".
  285.  
  286.   - reg
  287.       Usage: required
  288.       Value type: <prop-encoded-array>
  289.       Definition: A standard property.  Specifies the physical
  290.           address and length of the SEC4 configuration
  291.           registers.
  292.  
  293.    - interrupts
  294.       Usage: required
  295.       Value type: <prop_encoded-array>
  296.       Definition:  Specifies the interrupts generated by this
  297.            device.  The value of the interrupts property
  298.            consists of one interrupt specifier. The format
  299.            of the specifier is defined by the binding document
  300.            describing the node's interrupt parent.
  301.  
  302.    - interrupt-parent
  303.       Usage: (required if interrupt property is defined)
  304.       Value type: <phandle>
  305.       Definition: A single <phandle> value that points
  306.           to the interrupt parent to which the child domain
  307.           is being mapped.
  308.  
  309. EXAMPLE
  310.             compatible = "fsl,sec-v4.0-mon";
  311.             reg = <0x314000 0x1000>;
  312.             interrupt-parent = <&mpic>;
  313.             interrupts = <93 2>;
  314.       };
  315.  
  316. =====================================================================
  317. FULL EXAMPLE
  318.  
  319.       crypto: [email protected] {
  320.             compatible = "fsl,sec-v4.0";
  321.             #address-cells = <1>;
  322.             #size-cells = <1>;
  323.             reg = <0x300000 0x10000>;
  324.             ranges = <0 0x300000 0x10000>;
  325.             interrupt-parent = <&mpic>;
  326.             interrupts = <92 2>;
  327.  
  328.             sec_jr0: [email protected] {
  329.                   compatible = "fsl,sec-v4.0-job-ring";
  330.                   reg = <0x1000 0x1000>;
  331.                   interrupt-parent = <&mpic>;
  332.                   interrupts = <88 2>;
  333.             };
  334.  
  335.             sec_jr1: [email protected] {
  336.                   compatible = "fsl,sec-v4.0-job-ring";
  337.                   reg = <0x2000 0x1000>;
  338.                   interrupt-parent = <&mpic>;
  339.                   interrupts = <89 2>;
  340.             };
  341.  
  342.             sec_jr2: [email protected] {
  343.                   compatible = "fsl,sec-v4.0-job-ring";
  344.                   reg = <0x3000 0x1000>;
  345.                   interrupt-parent = <&mpic>;
  346.                   interrupts = <90 2>;
  347.             };
  348.  
  349.             sec_jr3: [email protected] {
  350.                   compatible = "fsl,sec-v4.0-job-ring";
  351.                   reg = <0x4000 0x1000>;
  352.                   interrupt-parent = <&mpic>;
  353.                   interrupts = <91 2>;
  354.             };
  355.  
  356.             [email protected] {
  357.                   compatible = "fsl,sec-v4.0-rtic";
  358.                   #address-cells = <1>;
  359.                   #size-cells = <1>;
  360.                   reg = <0x6000 0x100>;
  361.                   ranges = <0x0 0x6100 0xe00>;
  362.  
  363.                   rtic_a: [email protected] {
  364.                         compatible = "fsl,sec-v4.0-rtic-memory";
  365.                         reg = <0x00 0x20 0x100 0x80>;
  366.                   };
  367.  
  368.                   rtic_b: [email protected] {
  369.                         compatible = "fsl,sec-v4.0-rtic-memory";
  370.                         reg = <0x20 0x20 0x200 0x80>;
  371.                   };
  372.  
  373.                   rtic_c: [email protected] {
  374.                         compatible = "fsl,sec-v4.0-rtic-memory";
  375.                         reg = <0x40 0x20 0x300 0x80>;
  376.                   };
  377.  
  378.                   rtic_d: [email protected] {
  379.                         compatible = "fsl,sec-v4.0-rtic-memory";
  380.                         reg = <0x60 0x20 0x500 0x80>;
  381.                   };
  382.             };
  383.       };
  384.  
  385.       sec_mon: [email protected] {
  386.             compatible = "fsl,sec-v4.0-mon";
  387.             reg = <0x314000 0x1000>;
  388.             interrupt-parent = <&mpic>;
  389.             interrupts = <93 2>;
  390.       };
  391.  
  392. =====================================================================

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