TEXT 25
Fsl-sec2.txt Guest on 8th February 2021 09:25:41 AM
  1. Freescale SoC SEC Security Engines versions 2.x-3.x
  2.  
  3. Required properties:
  4.  
  5. - compatible : Should contain entries for this and backward compatible
  6.   SEC versions, high to low, e.g., "fsl,sec2.1", "fsl,sec2.0"
  7. - reg : Offset and length of the register set for the device
  8. - interrupts : the SEC's interrupt number
  9. - fsl,num-channels : An integer representing the number of channels
  10.   available.
  11. - fsl,channel-fifo-len : An integer representing the number of
  12.   descriptor pointers each channel fetch fifo can hold.
  13. - fsl,exec-units-mask : The bitmask representing what execution units
  14.   (EUs) are available. It's a single 32-bit cell. EU information
  15.   should be encoded following the SEC's Descriptor Header Dword
  16.   EU_SEL0 field documentation, i.e. as follows:
  17.  
  18.       bit 0  = reserved - should be 0
  19.       bit 1  = set if SEC has the ARC4 EU (AFEU)
  20.       bit 2  = set if SEC has the DES/3DES EU (DEU)
  21.       bit 3  = set if SEC has the message digest EU (MDEU/MDEU-A)
  22.       bit 4  = set if SEC has the random number generator EU (RNG)
  23.       bit 5  = set if SEC has the public key EU (PKEU)
  24.       bit 6  = set if SEC has the AES EU (AESU)
  25.       bit 7  = set if SEC has the Kasumi EU (KEU)
  26.       bit 8  = set if SEC has the CRC EU (CRCU)
  27.       bit 11 = set if SEC has the message digest EU extended alg set (MDEU-B)
  28.  
  29. remaining bits are reserved for future SEC EUs.
  30.  
  31. - fsl,descriptor-types-mask : The bitmask representing what descriptors
  32.   are available. It's a single 32-bit cell. Descriptor type information
  33.   should be encoded following the SEC's Descriptor Header Dword DESC_TYPE
  34.   field documentation, i.e. as follows:
  35.  
  36.       bit 0  = set if SEC supports the aesu_ctr_nonsnoop desc. type
  37.       bit 1  = set if SEC supports the ipsec_esp descriptor type
  38.       bit 2  = set if SEC supports the common_nonsnoop desc. type
  39.       bit 3  = set if SEC supports the 802.11i AES ccmp desc. type
  40.       bit 4  = set if SEC supports the hmac_snoop_no_afeu desc. type
  41.       bit 5  = set if SEC supports the srtp descriptor type
  42.       bit 6  = set if SEC supports the non_hmac_snoop_no_afeu desc.type
  43.       bit 7  = set if SEC supports the pkeu_assemble descriptor type
  44.       bit 8  = set if SEC supports the aesu_key_expand_output desc.type
  45.       bit 9  = set if SEC supports the pkeu_ptmul descriptor type
  46.       bit 10 = set if SEC supports the common_nonsnoop_afeu desc. type
  47.       bit 11 = set if SEC supports the pkeu_ptadd_dbl descriptor type
  48.  
  49.   ..and so on and so forth.
  50.  
  51. Optional properties:
  52.  
  53. - interrupt-parent : the phandle for the interrupt controller that
  54.   services interrupts for this device.
  55.  
  56. Example:
  57.  
  58.       /* MPC8548E */
  59.             compatible = "fsl,sec2.1", "fsl,sec2.0";
  60.             reg = <0x30000 0x10000>;
  61.             interrupts = <29 2>;
  62.             interrupt-parent = <&mpic>;
  63.             fsl,num-channels = <4>;
  64.             fsl,channel-fifo-len = <24>;
  65.             fsl,exec-units-mask = <0xfe>;
  66.             fsl,descriptor-types-mask = <0x12b0ebf>;
  67.       };

Paste is for source code and general debugging text.

Login or Register to edit, delete and keep track of your pastes and more.

Raw Paste

Login or Register to edit or fork this paste. It's free.