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Qualcomm adreno snapdragon display controller

Guest on 5th June 2022 03:38:25 AM

  1. Qualcomm adreno/snapdragon display controller
  2.  
  3. Required properties:
  4. - compatible:
  5.   * "qcom,mdp" - mdp4
  6. - reg: Physical base address and length of the controller's registers.
  7. - interrupts: The interrupt signal from the display controller.
  8. - connectors: array of phandles for output device(s)
  9. - clocks: device clocks
  10.   See ../clocks/clock-bindings.txt for details.
  11. - clock-names: the following clocks are required:
  12.   * "core_clk"
  13.   * "iface_clk"
  14.   * "lut_clk"
  15.   * "src_clk"
  16.   * "hdmi_clk"
  17.   * "mpd_clk"
  18.  
  19. Optional properties:
  20. - gpus: phandle for gpu device
  21.  
  22. Example:
  23.  
  24. / {
  25.         ...
  26.  
  27.         mdp: qcom,mdp@5100000 {
  28.                 compatible = "qcom,mdp";
  29.                 reg = <0x05100000 0xf0000>;
  30.                 interrupts = <GIC_SPI 75 0>;
  31.                 connectors = <&hdmi>;
  32.                 gpus = <&gpu>;
  33.                 clock-names =
  34.                     "core_clk",
  35.                     "iface_clk",
  36.                     "lut_clk",
  37.                     "src_clk",
  38.                     "hdmi_clk",
  39.                     "mdp_clk";
  40.                 clocks =
  41.                     <&mmcc MDP_SRC>,
  42.                     <&mmcc MDP_AHB_CLK>,
  43.                     <&mmcc MDP_LUT_CLK>,
  44.                     <&mmcc TV_SRC>,
  45.                     <&mmcc HDMI_TV_CLK>,
  46.                     <&mmcc MDP_TV_CLK>;
  47.         };
  48. };

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