C   28

Defines x86 CPU feature bits

Guest on 7th June 2022 01:20:54 AM

  1. /*
  2.  * Defines x86 CPU feature bits
  3.  */
  4. #ifndef _ASM_X86_CPUFEATURE_H
  5. #define _ASM_X86_CPUFEATURE_H
  6.  
  7. #include <asm/required-features.h>
  8.  
  9. #define NCAPINTS        9       /* N 32-bit words worth of info */
  10. /*
  11.  * KABI prevents us from extending NCAPINTS.  Instead use RH_EXT_NCAPINTS and
  12.  *  extend the array in the non-whitelisted cpuinfo_x86_rh structure.
  13.  */
  14. #define RH_EXT_NCAPINTS 1
  15. #define RHNCAPINTS      (NCAPINTS + RH_EXT_NCAPINTS)
  16.  
  17. /*
  18.  * Note: If the comment begins with a quoted string, that string is used
  19.  * in /proc/cpuinfo instead of the macro name.  If the string is "",
  20.  * this feature bit is not displayed in /proc/cpuinfo at all.
  21.  */
  22.  
  23. /* Intel-defined CPU features, CPUID level 0x00000001 (edx), word 0 */
  24. #define X86_FEATURE_FPU         (0*32+ 0) /* Onboard FPU */
  25. #define X86_FEATURE_VME         (0*32+ 1) /* Virtual Mode Extensions */
  26. #define X86_FEATURE_DE          (0*32+ 2) /* Debugging Extensions */
  27. #define X86_FEATURE_PSE         (0*32+ 3) /* Page Size Extensions */
  28. #define X86_FEATURE_TSC         (0*32+ 4) /* Time Stamp Counter */
  29. #define X86_FEATURE_MSR         (0*32+ 5) /* Model-Specific Registers */
  30. #define X86_FEATURE_PAE         (0*32+ 6) /* Physical Address Extensions */
  31. #define X86_FEATURE_MCE         (0*32+ 7) /* Machine Check Exception */
  32. #define X86_FEATURE_CX8         (0*32+ 8) /* CMPXCHG8 instruction */
  33. #define X86_FEATURE_APIC        (0*32+ 9) /* Onboard APIC */
  34. #define X86_FEATURE_SEP         (0*32+11) /* SYSENTER/SYSEXIT */
  35. #define X86_FEATURE_MTRR        (0*32+12) /* Memory Type Range Registers */
  36. #define X86_FEATURE_PGE         (0*32+13) /* Page Global Enable */
  37. #define X86_FEATURE_MCA         (0*32+14) /* Machine Check Architecture */
  38. #define X86_FEATURE_CMOV        (0*32+15) /* CMOV instructions */
  39.                                           /* (plus FCMOVcc, FCOMI with FPU) */
  40. #define X86_FEATURE_PAT         (0*32+16) /* Page Attribute Table */
  41. #define X86_FEATURE_PSE36       (0*32+17) /* 36-bit PSEs */
  42. #define X86_FEATURE_PN          (0*32+18) /* Processor serial number */
  43. #define X86_FEATURE_CLFLSH      (0*32+19) /* "clflush" CLFLUSH instruction */
  44. #define X86_FEATURE_DS          (0*32+21) /* "dts" Debug Store */
  45. #define X86_FEATURE_ACPI        (0*32+22) /* ACPI via MSR */
  46. #define X86_FEATURE_MMX         (0*32+23) /* Multimedia Extensions */
  47. #define X86_FEATURE_FXSR        (0*32+24) /* FXSAVE/FXRSTOR, CR4.OSFXSR */
  48. #define X86_FEATURE_XMM         (0*32+25) /* "sse" */
  49. #define X86_FEATURE_XMM2        (0*32+26) /* "sse2" */
  50. #define X86_FEATURE_SELFSNOOP   (0*32+27) /* "ss" CPU self snoop */
  51. #define X86_FEATURE_HT          (0*32+28) /* Hyper-Threading */
  52. #define X86_FEATURE_ACC         (0*32+29) /* "tm" Automatic clock control */
  53. #define X86_FEATURE_IA64        (0*32+30) /* IA-64 processor */
  54. #define X86_FEATURE_PBE         (0*32+31) /* Pending Break Enable */
  55.  
  56. /* AMD-defined CPU features, CPUID level 0x80000001, word 1 */
  57. /* Don't duplicate feature flags which are redundant with Intel! */
  58. #define X86_FEATURE_SYSCALL     (1*32+11) /* SYSCALL/SYSRET */
  59. #define X86_FEATURE_MP          (1*32+19) /* MP Capable. */
  60. #define X86_FEATURE_NX          (1*32+20) /* Execute Disable */
  61. #define X86_FEATURE_MMXEXT      (1*32+22) /* AMD MMX extensions */
  62. #define X86_FEATURE_FXSR_OPT    (1*32+25) /* FXSAVE/FXRSTOR optimizations */
  63. #define X86_FEATURE_GBPAGES     (1*32+26) /* "pdpe1gb" GB pages */
  64. #define X86_FEATURE_RDTSCP      (1*32+27) /* RDTSCP */
  65. #define X86_FEATURE_LM          (1*32+29) /* Long Mode (x86-64) */
  66. #define X86_FEATURE_3DNOWEXT    (1*32+30) /* AMD 3DNow! extensions */
  67. #define X86_FEATURE_3DNOW       (1*32+31) /* 3DNow! */
  68.  
  69. /* Transmeta-defined CPU features, CPUID level 0x80860001, word 2 */
  70. #define X86_FEATURE_RECOVERY    (2*32+ 0) /* CPU in recovery mode */
  71. #define X86_FEATURE_LONGRUN     (2*32+ 1) /* Longrun power control */
  72. #define X86_FEATURE_LRTI        (2*32+ 3) /* LongRun table interface */
  73.  
  74. /* Other features, Linux-defined mapping, word 3 */
  75. /* This range is used for feature bits which conflict or are synthesized */
  76. #define X86_FEATURE_CXMMX       (3*32+ 0) /* Cyrix MMX extensions */
  77. #define X86_FEATURE_K6_MTRR     (3*32+ 1) /* AMD K6 nonstandard MTRRs */
  78. #define X86_FEATURE_CYRIX_ARR   (3*32+ 2) /* Cyrix ARRs (= MTRRs) */
  79. #define X86_FEATURE_CENTAUR_MCR (3*32+ 3) /* Centaur MCRs (= MTRRs) */
  80. /* cpu types for specific tunings: */
  81. #define X86_FEATURE_K8          (3*32+ 4) /* "" Opteron, Athlon64 */
  82. #define X86_FEATURE_K7          (3*32+ 5) /* "" Athlon */
  83. #define X86_FEATURE_P3          (3*32+ 6) /* "" P3 */
  84. #define X86_FEATURE_P4          (3*32+ 7) /* "" P4 */
  85. #define X86_FEATURE_CONSTANT_TSC (3*32+ 8) /* TSC ticks at a constant rate */
  86. #define X86_FEATURE_UP          (3*32+ 9) /* smp kernel running on up */
  87. #define X86_FEATURE_FXSAVE_LEAK (3*32+10) /* "" FXSAVE leaks FOP/FIP/FOP */
  88. #define X86_FEATURE_ARCH_PERFMON (3*32+11) /* Intel Architectural PerfMon */
  89. #define X86_FEATURE_PEBS        (3*32+12) /* Precise-Event Based Sampling */
  90. #define X86_FEATURE_BTS         (3*32+13) /* Branch Trace Store */
  91. #define X86_FEATURE_SYSCALL32   (3*32+14) /* "" syscall in ia32 userspace */
  92. #define X86_FEATURE_SYSENTER32  (3*32+15) /* "" sysenter in ia32 userspace */
  93. #define X86_FEATURE_REP_GOOD    (3*32+16) /* rep microcode works well */
  94. #define X86_FEATURE_MFENCE_RDTSC (3*32+17) /* "" Mfence synchronizes RDTSC */
  95. #define X86_FEATURE_LFENCE_RDTSC (3*32+18) /* "" Lfence synchronizes RDTSC */
  96. #define X86_FEATURE_11AP        (3*32+19) /* "" Bad local APIC aka 11AP */
  97. #define X86_FEATURE_NOPL        (3*32+20) /* The NOPL (0F 1F) instructions */
  98. #define X86_FEATURE_AMDC1E      (3*32+21) /* AMD C1E detected */
  99. #define X86_FEATURE_XTOPOLOGY   (3*32+22) /* cpu topology enum extensions */
  100. #define X86_FEATURE_TSC_RELIABLE (3*32+23) /* TSC is known to be reliable */
  101. #define X86_FEATURE_NONSTOP_TSC (3*32+24) /* TSC does not stop in C states */
  102. #define X86_FEATURE_CLFLUSH_MONITOR (3*32+25) /* "" clflush reqd with monitor */
  103. #define X86_FEATURE_EXTD_APICID (3*32+26) /* has extended APICID (8 bits) */
  104. #define X86_FEATURE_AMD_DCM     (3*32+27) /* multi-node processor */
  105. #define X86_FEATURE_APERFMPERF  (3*32+28) /* APERFMPERF */
  106. #define X86_FEATURE_UNFAIR_SPINLOCK (3*32+29) /* use unfair spinlocks */
  107.  
  108. /* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */
  109. #define X86_FEATURE_XMM3        (4*32+ 0) /* "pni" SSE-3 */
  110. #define X86_FEATURE_PCLMULQDQ   (4*32+ 1) /* PCLMULQDQ instruction */
  111. #define X86_FEATURE_DTES64      (4*32+ 2) /* 64-bit Debug Store */
  112. #define X86_FEATURE_MWAIT       (4*32+ 3) /* "monitor" Monitor/Mwait support */
  113. #define X86_FEATURE_DSCPL       (4*32+ 4) /* "ds_cpl" CPL Qual. Debug Store */
  114. #define X86_FEATURE_VMX         (4*32+ 5) /* Hardware virtualization */
  115. #define X86_FEATURE_SMX         (4*32+ 6) /* Safer mode */
  116. #define X86_FEATURE_EST         (4*32+ 7) /* Enhanced SpeedStep */
  117. #define X86_FEATURE_TM2         (4*32+ 8) /* Thermal Monitor 2 */
  118. #define X86_FEATURE_SSSE3       (4*32+ 9) /* Supplemental SSE-3 */
  119. #define X86_FEATURE_CID         (4*32+10) /* Context ID */
  120. #define X86_FEATURE_FMA         (4*32+12) /* Fused multiply-add */
  121. #define X86_FEATURE_CX16        (4*32+13) /* CMPXCHG16B */
  122. #define X86_FEATURE_XTPR        (4*32+14) /* Send Task Priority Messages */
  123. #define X86_FEATURE_PDCM        (4*32+15) /* Performance Capabilities */
  124. #define X86_FEATURE_PCID        (4*32+17) /* Process Context Identifiers */
  125. #define X86_FEATURE_DCA         (4*32+18) /* Direct Cache Access */
  126. #define X86_FEATURE_XMM4_1      (4*32+19) /* "sse4_1" SSE-4.1 */
  127. #define X86_FEATURE_XMM4_2      (4*32+20) /* "sse4_2" SSE-4.2 */
  128. #define X86_FEATURE_X2APIC      (4*32+21) /* x2APIC */
  129. #define X86_FEATURE_MOVBE       (4*32+22) /* MOVBE instruction */
  130. #define X86_FEATURE_POPCNT      (4*32+23) /* POPCNT instruction */
  131. #define X86_FEATURE_TSC_DEADLINE_TIMER  (4*32+24) /* Tsc deadline timer */
  132. #define X86_FEATURE_AES         (4*32+25) /* AES instructions */
  133. #define X86_FEATURE_XSAVE       (4*32+26) /* XSAVE/XRSTOR/XSETBV/XGETBV */
  134. #define X86_FEATURE_OSXSAVE     (4*32+27) /* "" XSAVE enabled in the OS */
  135. #define X86_FEATURE_AVX         (4*32+28) /* Advanced Vector Extensions */
  136. #define X86_FEATURE_F16C        (4*32+29) /* 16-bit fp conversions */
  137. #define X86_FEATURE_RDRAND      (4*32+30) /* The RDRAND instruction */
  138. #define X86_FEATURE_HYPERVISOR  (4*32+31) /* Running on a hypervisor */
  139.  
  140. /* VIA/Cyrix/Centaur-defined CPU features, CPUID level 0xC0000001, word 5 */
  141. #define X86_FEATURE_XSTORE      (5*32+ 2) /* "rng" RNG present (xstore) */
  142. #define X86_FEATURE_XSTORE_EN   (5*32+ 3) /* "rng_en" RNG enabled */
  143. #define X86_FEATURE_XCRYPT      (5*32+ 6) /* "ace" on-CPU crypto (xcrypt) */
  144. #define X86_FEATURE_XCRYPT_EN   (5*32+ 7) /* "ace_en" on-CPU crypto enabled */
  145. #define X86_FEATURE_ACE2        (5*32+ 8) /* Advanced Cryptography Engine v2 */
  146. #define X86_FEATURE_ACE2_EN     (5*32+ 9) /* ACE v2 enabled */
  147. #define X86_FEATURE_PHE         (5*32+10) /* PadLock Hash Engine */
  148. #define X86_FEATURE_PHE_EN      (5*32+11) /* PHE enabled */
  149. #define X86_FEATURE_PMM         (5*32+12) /* PadLock Montgomery Multiplier */
  150. #define X86_FEATURE_PMM_EN      (5*32+13) /* PMM enabled */
  151.  
  152. /* More extended AMD flags: CPUID level 0x80000001, ecx, word 6 */
  153. #define X86_FEATURE_LAHF_LM     (6*32+ 0) /* LAHF/SAHF in long mode */
  154. #define X86_FEATURE_CMP_LEGACY  (6*32+ 1) /* If yes HyperThreading not valid */
  155. #define X86_FEATURE_SVM         (6*32+ 2) /* Secure virtual machine */
  156. #define X86_FEATURE_EXTAPIC     (6*32+ 3) /* Extended APIC space */
  157. #define X86_FEATURE_CR8_LEGACY  (6*32+ 4) /* CR8 in 32-bit mode */
  158. #define X86_FEATURE_ABM         (6*32+ 5) /* Advanced bit manipulation */
  159. #define X86_FEATURE_SSE4A       (6*32+ 6) /* SSE-4A */
  160. #define X86_FEATURE_MISALIGNSSE (6*32+ 7) /* Misaligned SSE mode */
  161. #define X86_FEATURE_3DNOWPREFETCH (6*32+ 8) /* 3DNow prefetch instructions */
  162. #define X86_FEATURE_OSVW        (6*32+ 9) /* OS Visible Workaround */
  163. #define X86_FEATURE_IBS         (6*32+10) /* Instruction Based Sampling */
  164. #define X86_FEATURE_XOP         (6*32+11) /* extended AVX instructions */
  165. #define X86_FEATURE_SKINIT      (6*32+12) /* SKINIT/STGI instructions */
  166. #define X86_FEATURE_WDT         (6*32+13) /* Watchdog timer */
  167. #define X86_FEATURE_LWP         (6*32+15) /* Light Weight Profiling */
  168. #define X86_FEATURE_FMA4        (6*32+16) /* 4 operands MAC instructions */
  169. #define X86_FEATURE_TCE         (6*32+17) /* translation cache extension */
  170. #define X86_FEATURE_NODEID_MSR  (6*32+19) /* NodeId MSR */
  171. #define X86_FEATURE_TBM         (6*32+21) /* trailing bit manipulations */
  172. #define X86_FEATURE_TOPOEXT     (6*32+22) /* topology extensions CPUID leafs */
  173. #define X86_FEATURE_PERFCTR_CORE (6*32+23) /* core performance counter extensions */
  174. #define X86_FEATURE_PERFCTR_NB  (6*32+24) /* NB performance counter extensions */
  175. #define X86_FEATURE_PERFCTR_L2  (6*32+28) /* L2 performance counter extensions */
  176.  
  177. /*
  178.  * Auxiliary flags: Linux defined - For features scattered in various
  179.  * CPUID levels like 0x6, 0xA etc, word 7
  180.  */
  181. #define X86_FEATURE_IDA         (7*32+ 0) /* Intel Dynamic Acceleration */
  182. #define X86_FEATURE_ARAT        (7*32+ 1) /* Always Running APIC Timer */
  183. #define X86_FEATURE_CPB         (7*32+ 2) /* AMD Core Performance Boost */
  184. #define X86_FEATURE_EPB         (7*32+ 3) /* IA32_ENERGY_PERF_BIAS support */
  185. #define X86_FEATURE_XSAVEOPT    (7*32+ 4) /* Optimized Xsave */
  186. #define X86_FEATURE_PLN         (7*32+ 5) /* Intel Power Limit Notification */
  187. #define X86_FEATURE_PTS         (7*32+ 6) /* Intel Package Thermal Status */
  188. #define X86_FEATURE_DTS         (7*32+ 7) /* Digital Thermal Sensor */
  189.  
  190. /* Virtualization flags: Linux defined, word 8 */
  191. #define X86_FEATURE_TPR_SHADOW  (8*32+ 0) /* Intel TPR Shadow */
  192. #define X86_FEATURE_VNMI        (8*32+ 1) /* Intel Virtual NMI */
  193. #define X86_FEATURE_FLEXPRIORITY (8*32+ 2) /* Intel FlexPriority */
  194. #define X86_FEATURE_EPT         (8*32+ 3) /* Intel Extended Page Table */
  195. #define X86_FEATURE_VPID        (8*32+ 4) /* Intel Virtual Processor ID */
  196. #define X86_FEATURE_NPT         (8*32+5)  /* AMD Nested Page Table support */
  197. #define X86_FEATURE_LBRV        (8*32+6)  /* AMD LBR Virtualization support */
  198. #define X86_FEATURE_SVML        (8*32+7)  /* "svm_lock" AMD SVM locking MSR */
  199. #define X86_FEATURE_NRIPS       (8*32+8)  /* "nrip_save" AMD SVM next_rip save */
  200. #define X86_FEATURE_TSCRATEMSR  (8*32+ 9) /* "tsc_scale" AMD TSC scaling support */
  201. #define X86_FEATURE_VMCBCLEAN   (8*32+10) /* "vmcb_clean" AMD VMCB clean bits support */
  202. #define X86_FEATURE_FLUSHBYASID (8*32+11) /* AMD flush-by-ASID support */
  203. #define X86_FEATURE_DECODEASSISTS (8*32+12) /* AMD Decode Assists support */
  204. #define X86_FEATURE_PAUSEFILTER (8*32+13) /* AMD filtered pause intercept */
  205. #define X86_FEATURE_PFTHRESHOLD (8*32+14) /* AMD pause filter threshold */
  206.  
  207. /* Intel-defined CPU features, CPUID level 0x00000007:0 (ebx), word 9 */
  208. #define X86_FEATURE_FSGSBASE    (9*32+ 0) /* {RD/WR}{FS/GS}BASE instructions*/
  209. #define X86_FEATURE_BMI1        (9*32+ 3) /* 1st group bit manipulation extensions */
  210. #define X86_FEATURE_HLE         (9*32+ 4) /* Hardware Lock Elision */
  211. #define X86_FEATURE_AVX2        (9*32+ 5) /* AVX2 instructions */
  212. #define X86_FEATURE_SMEP        (9*32+ 7) /* Supervisor Mode Execution Protection */
  213. #define X86_FEATURE_BMI2        (9*32+ 8) /* 2nd group bit manipulation extensions */
  214. #define X86_FEATURE_ERMS        (9*32+ 9) /* Enhanced REP MOVSB/STOSB */
  215. #define X86_FEATURE_INVPCID     (9*32+10) /* Invalidate Processor Context ID */
  216. #define X86_FEATURE_RTM         (9*32+11) /* Restricted Transactional Memory */
  217. #define X86_FEATURE_AVX512F     (9*32+16) /* AVX-512 Foundation */
  218. #define X86_FEATURE_AVX512PF    (9*32+26) /* AVX-512 Prefetch */
  219. #define X86_FEATURE_AVX512ER    (9*32+27) /* AVX-512 Exponential and Reciprocal */
  220. #define X86_FEATURE_AVX512CD    (9*32+28) /* AVX-512 Conflict Detection */
  221. #define X86_FEATURE_RDSEED      (9*32+18) /* The RDSEED instruction */
  222. #define X86_FEATURE_ADX         (9*32+19) /* The ADCX and ADOX instructions */
  223.  
  224. #if defined(__KERNEL__) && !defined(__ASSEMBLY__)
  225.  
  226. #include <asm/asm.h>
  227. #include <linux/bitops.h>
  228.  
  229. extern const char * const x86_cap_flags[RHNCAPINTS*32];
  230. extern const char * const x86_power_flags[32];
  231.  
  232.  /* start of RH extended capabilities word 9, bit 0 */
  233. #define RH_EXT_CAP_BIT0 (9*32+0)
  234.  
  235. /*
  236.  * RHEL: If the bit is in the cpuinfo_x86 struct (ie, is word 8 or less),
  237.  * then just use the bit like it always has been.  If it is in the new
  238.  * extended struct, cpuinfo_x86_rh, then check to see if the cpuinfo_x86
  239.  * struct was the boot_cpu_data struct.  If it was the boot_cpu_data
  240.  * struct then use boot_cpu_data_rh, o/w use the cpu_data_rh per_cpu data
  241.  */
  242. #define _cpu_cap_fn(func, c, bit)                                       \
  243.         ((bit < RH_EXT_CAP_BIT0) ?                                      \
  244.          func##_bit(bit, (unsigned long *)((c)->x86_capability)) :      \
  245.          ((c == &boot_cpu_data) ?                                       \
  246.           func##_bit(bit - RH_EXT_CAP_BIT0,                             \
  247.                      (unsigned long *)boot_cpu_data_rh.x86_capability): \
  248.           func##_bit(bit - RH_EXT_CAP_BIT0,                             \
  249.                  (unsigned long *)cpu_data_rh((c)->cpu_index).x86_capability)\
  250.          )                                                              \
  251.         )
  252.  
  253. #define test_cpu_cap(c, bit) _cpu_cap_fn(test, c, bit)
  254. #define set_cpu_cap(c, bit) _cpu_cap_fn(set, c, bit)
  255. #define clear_cpu_cap(c, bit) _cpu_cap_fn(clear, c, bit)
  256.  
  257. #define cpu_has(c, bit)                                                 \
  258.         (__builtin_constant_p(bit) &&                                   \
  259.          ( (((bit)>>5)==0 && (1UL<<((bit)&31) & REQUIRED_MASK0)) ||     \
  260.            (((bit)>>5)==1 && (1UL<<((bit)&31) & REQUIRED_MASK1)) ||     \
  261.            (((bit)>>5)==2 && (1UL<<((bit)&31) & REQUIRED_MASK2)) ||     \
  262.            (((bit)>>5)==3 && (1UL<<((bit)&31) & REQUIRED_MASK3)) ||     \
  263.            (((bit)>>5)==4 && (1UL<<((bit)&31) & REQUIRED_MASK4)) ||     \
  264.            (((bit)>>5)==5 && (1UL<<((bit)&31) & REQUIRED_MASK5)) ||     \
  265.            (((bit)>>5)==6 && (1UL<<((bit)&31) & REQUIRED_MASK6)) ||     \
  266.            (((bit)>>5)==7 && (1UL<<((bit)&31) & REQUIRED_MASK7)) ||     \
  267.            (((bit)>>5)==8 && (1UL<<((bit)&31) & REQUIRED_MASK8)) ||     \
  268.            (((bit)>>5)==9 && (1UL<<((bit)&31) & REQUIRED_MASK9)) )      \
  269.           ? 1 :                                                         \
  270.          test_cpu_cap(c, bit))
  271.  
  272. #define this_cpu_has(bit)                                               \
  273.         cpu_has(&current_cpu_data, bit)
  274.  
  275. #define boot_cpu_has(bit)       cpu_has(&boot_cpu_data, bit)
  276.  
  277. #define setup_clear_cpu_cap(bit) do { \
  278.         clear_cpu_cap(&boot_cpu_data, bit);     \
  279.         set_bit(bit, (unsigned long *)cpu_caps_cleared); \
  280. } while (0)
  281. #define setup_force_cpu_cap(bit) do { \
  282.         set_cpu_cap(&boot_cpu_data, bit);       \
  283.         set_bit(bit, (unsigned long *)cpu_caps_set);    \
  284. } while (0)
  285.  
  286. #define cpu_has_fpu             boot_cpu_has(X86_FEATURE_FPU)
  287. #define cpu_has_vme             boot_cpu_has(X86_FEATURE_VME)
  288. #define cpu_has_de              boot_cpu_has(X86_FEATURE_DE)
  289. #define cpu_has_pse             boot_cpu_has(X86_FEATURE_PSE)
  290. #define cpu_has_tsc             boot_cpu_has(X86_FEATURE_TSC)
  291. #define cpu_has_pae             boot_cpu_has(X86_FEATURE_PAE)
  292. #define cpu_has_pge             boot_cpu_has(X86_FEATURE_PGE)
  293. #define cpu_has_apic            boot_cpu_has(X86_FEATURE_APIC)
  294. #define cpu_has_sep             boot_cpu_has(X86_FEATURE_SEP)
  295. #define cpu_has_mtrr            boot_cpu_has(X86_FEATURE_MTRR)
  296. #define cpu_has_mmx             boot_cpu_has(X86_FEATURE_MMX)
  297. #define cpu_has_fxsr            boot_cpu_has(X86_FEATURE_FXSR)
  298. #define cpu_has_xmm             boot_cpu_has(X86_FEATURE_XMM)
  299. #define cpu_has_xmm2            boot_cpu_has(X86_FEATURE_XMM2)
  300. #define cpu_has_xmm3            boot_cpu_has(X86_FEATURE_XMM3)
  301. #define cpu_has_ssse3           boot_cpu_has(X86_FEATURE_SSSE3)
  302. #define cpu_has_aes             boot_cpu_has(X86_FEATURE_AES)
  303. #define cpu_has_avx             boot_cpu_has(X86_FEATURE_AVX)
  304. #define cpu_has_ht              boot_cpu_has(X86_FEATURE_HT)
  305. #define cpu_has_mp              boot_cpu_has(X86_FEATURE_MP)
  306. #define cpu_has_nx              boot_cpu_has(X86_FEATURE_NX)
  307. #define cpu_has_k6_mtrr         boot_cpu_has(X86_FEATURE_K6_MTRR)
  308. #define cpu_has_cyrix_arr       boot_cpu_has(X86_FEATURE_CYRIX_ARR)
  309. #define cpu_has_centaur_mcr     boot_cpu_has(X86_FEATURE_CENTAUR_MCR)
  310. #define cpu_has_xstore          boot_cpu_has(X86_FEATURE_XSTORE)
  311. #define cpu_has_xstore_enabled  boot_cpu_has(X86_FEATURE_XSTORE_EN)
  312. #define cpu_has_xcrypt          boot_cpu_has(X86_FEATURE_XCRYPT)
  313. #define cpu_has_xcrypt_enabled  boot_cpu_has(X86_FEATURE_XCRYPT_EN)
  314. #define cpu_has_ace2            boot_cpu_has(X86_FEATURE_ACE2)
  315. #define cpu_has_ace2_enabled    boot_cpu_has(X86_FEATURE_ACE2_EN)
  316. #define cpu_has_phe             boot_cpu_has(X86_FEATURE_PHE)
  317. #define cpu_has_phe_enabled     boot_cpu_has(X86_FEATURE_PHE_EN)
  318. #define cpu_has_pmm             boot_cpu_has(X86_FEATURE_PMM)
  319. #define cpu_has_pmm_enabled     boot_cpu_has(X86_FEATURE_PMM_EN)
  320. #define cpu_has_ds              boot_cpu_has(X86_FEATURE_DS)
  321. #define cpu_has_pebs            boot_cpu_has(X86_FEATURE_PEBS)
  322. #define cpu_has_clflush         boot_cpu_has(X86_FEATURE_CLFLSH)
  323. #define cpu_has_bts             boot_cpu_has(X86_FEATURE_BTS)
  324. #define cpu_has_gbpages         boot_cpu_has(X86_FEATURE_GBPAGES)
  325. #define cpu_has_arch_perfmon    boot_cpu_has(X86_FEATURE_ARCH_PERFMON)
  326. #define cpu_has_pat             boot_cpu_has(X86_FEATURE_PAT)
  327. #define cpu_has_xmm4_1          boot_cpu_has(X86_FEATURE_XMM4_1)
  328. #define cpu_has_xmm4_2          boot_cpu_has(X86_FEATURE_XMM4_2)
  329. #define cpu_has_x2apic          boot_cpu_has(X86_FEATURE_X2APIC)
  330. #define cpu_has_xsave           boot_cpu_has(X86_FEATURE_XSAVE)
  331. #define cpu_has_osxsave         boot_cpu_has(X86_FEATURE_OSXSAVE)
  332. #define cpu_has_hypervisor      boot_cpu_has(X86_FEATURE_HYPERVISOR)
  333. #define cpu_has_pclmulqdq       boot_cpu_has(X86_FEATURE_PCLMULQDQ)
  334. #define cpu_has_perfctr_core    boot_cpu_has(X86_FEATURE_PERFCTR_CORE)
  335. #define cpu_has_perfctr_nb      boot_cpu_has(X86_FEATURE_PERFCTR_NB)
  336. #define cpu_has_topoext         boot_cpu_has(X86_FEATURE_TOPOEXT)
  337. #define cpu_has_perfctr_l2      boot_cpu_has(X86_FEATURE_PERFCTR_L2)
  338.  
  339. #if defined(CONFIG_X86_INVLPG) || defined(CONFIG_X86_64)
  340. # define cpu_has_invlpg         1
  341. #else
  342. # define cpu_has_invlpg         (boot_cpu_data.x86 > 3)
  343. #endif
  344.  
  345. #ifdef CONFIG_X86_64
  346.  
  347. #undef  cpu_has_vme
  348. #define cpu_has_vme             0
  349.  
  350. #undef  cpu_has_pae
  351. #define cpu_has_pae             ___BUG___
  352.  
  353. #undef  cpu_has_mp
  354. #define cpu_has_mp              1
  355.  
  356. #undef  cpu_has_k6_mtrr
  357. #define cpu_has_k6_mtrr         0
  358.  
  359. #undef  cpu_has_cyrix_arr
  360. #define cpu_has_cyrix_arr       0
  361.  
  362. #undef  cpu_has_centaur_mcr
  363. #define cpu_has_centaur_mcr     0
  364.  
  365. #endif /* CONFIG_X86_64 */
  366.  
  367. /*
  368.  * Static testing of CPU features.  Used the same as boot_cpu_has().
  369.  * These are only valid after alternatives have run, but will statically
  370.  * patch the target code for additional performance.
  371.  *
  372.  */
  373. static __always_inline __pure bool __static_cpu_has(u16 bit)
  374. {
  375. #if __GNUC__ > 4 || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
  376.                 asm goto("1: jmp %l[t_no]\n"
  377.                          "2:\n"
  378.                          ".section .altinstructions,\"a\"\n"
  379.                          _ASM_ALIGN "\n"
  380.                          _ASM_PTR "1b\n"
  381.                          _ASM_PTR "0\n"         /* no replacement */
  382.                          " .word %P0\n"         /* feature bit */
  383.                          " .byte 2b - 1b\n"     /* source len */
  384.                          " .byte 0\n"           /* replacement len */
  385.                          ".previous\n"
  386.                          /* skipping size check since replacement size = 0 */
  387.                          : : "i" (bit) : : t_no);
  388.                 return true;
  389.         t_no:
  390.                 return false;
  391. #else
  392.                 u8 flag;
  393.                 /* Open-coded due to __stringify() in ALTERNATIVE() */
  394.                 asm volatile("1: movb $0,%0\n"
  395.                              "2:\n"
  396.                              ".section .altinstructions,\"a\"\n"
  397.                              _ASM_ALIGN "\n"
  398.                              _ASM_PTR "1b\n"
  399.                              _ASM_PTR "3f\n"
  400.                              " .word %P1\n"             /* feature bit */
  401.                              " .byte 2b - 1b\n"         /* source len */
  402.                              " .byte 4f - 3f\n"         /* replacement len */
  403.                              ".previous\n"
  404.                              ".section .discard,\"aw\",@progbits\n"
  405.                              " .byte 0xff + (4f-3f) - (2b-1b)\n" /* size check */
  406.                              ".previous\n"
  407.                              ".section .altinstr_replacement,\"ax\"\n"
  408.                              "3: movb $1,%0\n"
  409.                              "4:\n"
  410.                              ".previous\n"
  411.                              : "=qm" (flag) : "i" (bit));
  412.                 return flag;
  413. #endif
  414. }
  415.  
  416. #define static_cpu_has(bit)                                     \
  417. (                                                               \
  418.         __builtin_constant_p(boot_cpu_has(bit)) ?               \
  419.                 boot_cpu_has(bit) :                             \
  420.         __builtin_constant_p(bit) ?                             \
  421.                 __static_cpu_has(bit) :                         \
  422.                 boot_cpu_has(bit)                               \
  423. )
  424.  
  425. #endif /* defined(__KERNEL__) && !defined(__ASSEMBLY__) */
  426.  
  427. #endif /* _ASM_X86_CPUFEATURE_H */

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