TEXT   49

ARMulator configuration file

Guest on 11th July 2022 07:35:04 PM

  1. ;; ARMulator configuration file
  2. ;; Copyright (c)  ARM Limited. All Rights Reserved.
  3.  
  4. ;; RCS $Revision: 1.118.2.10 $
  5. ;; Revising $Author: lmacgreg $
  6.  
  7.  
  8. ;;
  9. ;; This is the configuration file for ARMulator ADS 1.0
  10. ;;
  11.  
  12. ;; Comment this out for benchmarking
  13. ; For the moment we assume that if no clock speed has been set on the
  14. ; command-line, the user wishes to use a wall-clock for timing
  15. #if !CPUSPEED
  16. Clock=Real
  17. #endif
  18.  
  19.  
  20. ;; This line controls whether (some) models give more useful descriptions
  21. ;; of what they are on startup, and during running.
  22. Verbose=False
  23.  
  24. ;; To get the full validation environment, we set Validate to one of
  25. ;; "OS" or "CP".  The former installs itself as an OS model, while
  26. ;; the latter simply registers the validation coprocessors.
  27. ;Validate=OS
  28. ;Validate=CP
  29.  
  30. ;; Newtrickbox tells the armulator that if trickbox memory is being used it
  31. ;; should use the new one.
  32. ;Newtrickbox=1
  33.  
  34. ;; To enable faster watchpoints, set "WatchpointsEnabled"
  35. WatchpointsEnabled=False
  36.  
  37. ;; ARMulator comes up with the cache and MMU enabled, when using a
  38. ;; cached Processor. To disable this, set 'UsePageTables' to 'False'.
  39. UsePageTables=True
  40.  
  41.  
  42.  
  43. ;; *****************************************************************
  44. ;; ARMulator Peripheral Models
  45. ;; Central list of peripherals
  46. ;; Use this list to enable/disable peripherals
  47. ;; *****************************************************************
  48. ;; To enable a peripheral change the rhs to True
  49. ;; To disable a peripheral change the rhs to False
  50.  
  51. TimerEnabled=True
  52. WDogEnabled=False
  53. IntCEnabled=True
  54. TubeEnabled=False
  55.  
  56. ; Note that DCC is enabled by default if running on a processor
  57. ; with an EmbeddedICE macrocell
  58.  
  59. ;; end of peripheral list
  60. ;; *****************************************************************
  61.  
  62.  
  63. ;; ARMulator can tell you how much stack your program uses (at a
  64. ;; substantial run-time cost)
  65. TrackStack=False
  66.  
  67.  
  68. #if Validate && Validate==OS
  69.  
  70. OS=ValidateOS
  71.  
  72. #else
  73.  
  74. ;; The default operating-system is Angel
  75. #if OSMODEL_Angel
  76. OS=Angel
  77. #else
  78. OS=Demon
  79. #endif
  80.  
  81. #endif
  82.  
  83. ;; Operating system (Angel) configuration
  84.  
  85. #if OS==Angel || OS==Demon
  86.  
  87. { OS
  88.  
  89. ;; Angel configuration
  90.  
  91. ;; SWIs to use for Angel
  92. AngelSWIARM=0x123456
  93. AngelSWIThumb=0xab
  94.  
  95.  
  96. #if PID7T
  97. HeapBase=0x02069000
  98. HeapLimit=0x02079000
  99. StackBase=0x02080000
  100. StackLimit=0x02079000
  101. #else
  102. HeapBase=0x0
  103. HeapLimit=0x07000000
  104. StackBase=0x08000000
  105. StackLimit=0x07000000
  106. #endif
  107.  
  108.  
  109. #if !FPE || FPE==False
  110. Demon=No
  111. FPE=No
  112. #else
  113. Demon=Yes
  114. #endif
  115.  
  116. ;; Demon configuration
  117.  
  118. ;; Configure the locations of stacks, etc.
  119. AddrSuperStack=0xa00
  120. AddrAbortStack=0x800
  121. AddrUndefStack=0x700
  122. AddrIRQStack=0x500
  123. AddrFIQStack=0x400
  124.  
  125. ;; The default location of the user mode stack
  126. AddrUserStack=0x80000
  127.  
  128. ;; Start of the "soft vector" code
  129. AddrSoftVectors=0xa40
  130.  
  131. ;; Where to place a copy of the command line
  132. AddrCmdLine=0xf00
  133.  
  134. ;; Address and workspace for installed handlers
  135. AddrsOfHandlers=0xad0
  136.  
  137. ;; Default handlers
  138. SoftVectorCode=0xb80
  139. }
  140. #endif
  141.  
  142.  
  143.  
  144.  
  145. ;;
  146. ;; This is the list of all processors supported by ARMulator.
  147. ;;
  148.  
  149. { Processors
  150.  
  151. Default=ARM7TDMI
  152.  
  153. ;; Entries are of the form:
  154. ;
  155. ; { <processor-name>
  156. ; ... features ...
  157. ; ... variants ...
  158. ; }
  159. ;
  160. ;; or
  161. ;
  162. ; <processor-variant>=<processor-name>
  163. ;
  164. ;; In the latter case, the "variant" must appear in the variants list
  165. ;; for the named processor.
  166.  
  167.  
  168. ;; The "BASIC" RDI model provides models of the ARM6/ARM7 and ARM8
  169. ;; families.
  170. #if RDI_BASIC
  171.  
  172.  
  173. ;; ARM6 family
  174.  
  175. { ARM6
  176. ;; Features:
  177. Processor=ARM6
  178. Core=ARM6
  179. ARMulator=BASIC
  180. Architecture=3
  181.  
  182. ;; Variants:
  183. ARM60:Processor=ARM60
  184.  
  185. ;; Cached variants
  186. ARM600:Processor=ARM600
  187. ARM610:Processor=ARM610
  188.  
  189. ARM600:Memory=ARM600
  190. ARM610:Memory=ARM610
  191. }
  192.  
  193. ARM60=ARM6
  194. #if MEMORY_MMUlator
  195. ARM600=ARM6
  196. ARM610=ARM6
  197. #endif
  198.  
  199. ;; ARM7 family
  200.  
  201. { ARM7
  202. ;; Features:
  203. Processor=ARM7
  204. Core=ARM7
  205. ARMulator=BASIC
  206. Architecture=3
  207. Nexec
  208. LateAborts
  209. SubPage
  210.  
  211.  
  212.  
  213. ;; Cached variants
  214. ARM704:Processor=ARM704
  215. ARM710a:Processor=ARM710a
  216. ARM710:Processor=ARM710
  217.  
  218. ;; MMU/PU properties - used by pagetable to determine how to start
  219.  
  220. ARM704:HASMMU
  221. ARM710a:HASMMU
  222. ARM710:HASMMU
  223.  
  224. ARM704:Memory=ARM704
  225. ARM710a:Memory=ARM710a
  226. ARM710:Memory=ARM710
  227. }
  228.  
  229.  
  230. #if MEMORY_MMUlator
  231. ARM704=ARM7
  232. ARM710=ARM7
  233. ARM710a=ARM7
  234. #endif
  235.  
  236. ;; ARM7D family - ARM7D
  237.  
  238. { ARM7D
  239. ;; Features
  240. Processor=ARM7D
  241. Core=ARM7
  242. ARMulator=BASIC
  243. Architecture=3
  244. Nexec
  245. LateAborts
  246. Debug
  247.  
  248.  
  249. ;; ARM7DM families
  250. ARM7DM:Processor=ARM7DM
  251. ARM7DM:Architecture=3M
  252.  
  253.  
  254. }
  255.  
  256. ARM7DM=ARM7D
  257.  
  258.  
  259. ;; Thumb family
  260.  
  261. { ARM7TDM
  262. ;; Features
  263. Processor=ARM7TDM
  264. Core=ARM7
  265. ARMulator=BASIC
  266. Architecture=4T
  267. Nexec
  268. LateAborts
  269. Debug
  270.  
  271. ARM7TDMI:Processor=ARM7TDMI
  272. ARM7TM:Processor=ARM7TM
  273.  
  274. ;; Cached variants
  275. ARM710T:Processor=ARM710T
  276. ARM710T:Memory=ARM710T
  277. ARM710T:HASMMU
  278.  
  279. ARM720T:Processor=ARM720T
  280. ARM720T:Memory=ARM720T
  281. ARM720T:HighExceptionVectors
  282. ARM720T:HASMMU
  283.  
  284. ARM740T:Processor=ARM740T
  285. ARM740T:Memory=ARM740T
  286. ARM740T:HASPU
  287. }
  288.  
  289. ARM7TM=ARM7TDM
  290. ARM7TDMI=ARM7TDM
  291. #if MEMORY_MMUlator
  292. ARM710T=ARM7TDM
  293. ARM720T=ARM7TDM
  294. ARM740T=ARM7TDM
  295. #endif
  296.  
  297. ;; Synthesisable ARM family
  298.  
  299. { ARM7TM-S
  300. ;; Features
  301. Processor=ARM7TM-S
  302. Core=ARM7
  303. ARMulator=BASIC
  304. Architecture=4T
  305. Nexec
  306. LateAborts
  307. Debug
  308.  
  309. ARM7TDMI-S:Processor=ARM7TDMI-S
  310.  
  311. ; Options - no long multipliers
  312.  
  313. ARM7T-S:Architecture=4TxM
  314. ARM7T-S:Processor=ARM7T-S
  315. ARM7T-S:EarlySignedMultiply=True
  316.  
  317. ARM7TDI-S:Architecture=4TxM
  318. ARM7TDI-S:Processor=ARM7TDI-S
  319. ARM7TDI-S:EarlySignedMultiply=True
  320.  
  321. }
  322.  
  323. ARM7T-S=ARM7TM-S
  324. ARM7TDI-S=ARM7TM-S
  325. ARM7TDMI-S=ARM7TM-S
  326.  
  327. ;; ARM8 family
  328.  
  329. { ARM8
  330. ;; Features:
  331. Processor=ARM8
  332. Core=ARM8
  333. ARMulator=BASIC
  334. Architecture=4
  335. Nexec
  336. MultipleEarlyAborts
  337. AbortsStopMultiple
  338. Prefetch
  339. HasBranchPrediction
  340. NoLDCSTC
  341.  
  342. ;; Variants:
  343. ARM810:Processor=ARM810
  344.  
  345. ARM810:Memory=ARM810
  346. }
  347.  
  348. #if MEMORY_MMUlator
  349. ARM810=ARM8
  350. #endif
  351. #endif
  352.  
  353.  
  354. ;; The "STRONG" RDI interface provides models of the StrongARM1 family.
  355. #if RDI_STRONG
  356.  
  357. ;; StrongARM family
  358.  
  359.  
  360. { StrongARM
  361. ;; Features:
  362. Processor=StrongARM
  363. Core=StrongARM
  364. ARMulator=STRONG
  365. Architecture=4
  366. Nexec
  367. MultipleEarlyAborts
  368. AbortsStopMultiple
  369. StrongARMAware
  370. NoLDCSTC
  371. NoCDP
  372.  
  373. ;; Variants:
  374. SA-110:Processor=SA-110
  375.  
  376. SA-110:Memory=SA-110
  377. }
  378.  
  379. #if MEMORY_StrongMMU
  380. SA-110=StrongARM
  381. #endif
  382.  
  383.  
  384. #endif
  385.  
  386.  
  387. ;; ARM9 family
  388.  
  389.  
  390. ;; ARM 9E variant
  391. { ARM9E
  392. ;; Features:
  393. Processor=ARM9E
  394. Core=ARM9
  395. ARMulator=ARM9ulator
  396. Architecture=4T
  397. Nexec
  398. MultipleEarlyAborts
  399. AbortsStopMultiple
  400. CoreCycles
  401. HighExceptionVectors
  402. ARM9Extensions
  403. ;;StrongARMAware
  404. ;;NoLDCSTC
  405. ;;NoCDP
  406.  
  407.  
  408. }
  409.  
  410.  
  411.  
  412. { ARM9TDMI
  413. ;; Features:
  414. Processor=ARM9TDMI
  415. Core=ARM9
  416. ARMulator=ARM9ulator
  417. Architecture=4T
  418. Nexec
  419. MultipleEarlyAborts
  420. AbortsStopMultiple
  421. CoreCycles
  422. HighExceptionVectors
  423. ;;StrongARMAware
  424. ;;NoLDCSTC
  425. ;;NoCDP
  426.  
  427. ;; Variants:
  428. { ARM940T
  429. Processor=ARM940T
  430. Memory=ARM940T
  431. HASPU
  432. }
  433. { ARM920T
  434. Processor=ARM920T
  435. Memory=ARM920T
  436. HASMMU
  437. }
  438. }
  439. #if MEMORY_ARM940CacheMPU
  440. ARM940T=ARM9TDMI
  441. #endif
  442. #if MEMORY_ARM920CacheMMU
  443. ARM920T=ARM9TDMI
  444. #endif
  445.  
  446. ;; New processors/variants can be added here.
  447. }
  448.  
  449.  
  450. ;;
  451. ;; List of memory models
  452. ;;
  453.  
  454. { Memories
  455.  
  456. ;; Default memory model is the "Flat" model, or the "MapFile" model if there
  457. ;; is an armsd.map file to load.
  458.  
  459. ;; Validation suite uses the trickbox
  460. #if Validate
  461. Default=TrickBox
  462. #endif
  463.  
  464. ;; If there's a memory mapfile, use that.
  465. #if UseMapFile
  466. #if UseMapFile==True && MEMORY_MapFile
  467. Default=MapFile
  468. #endif
  469. #endif
  470.  
  471. ;; Default default is the flat memory map
  472. Default=Flat
  473.  
  474. ;; The "MMUlator" provides emulation of the caches and MMU's on the
  475. ;; ARM6/ARM7 and ARM8 processor families.
  476.  
  477. #if MEMORY_MMUlator
  478. ;; Plumbing for cached models - leave alone
  479. ARM600=MMUlator
  480. ARM610=MMUlator
  481.  
  482.  
  483. ARM704=MMUlator
  484. ARM710=MMUlator
  485. ARM710a=MMUlator
  486. ARM710T=MMUlator
  487. ARM720T=MMUlator
  488. ARM740T=MMUlator
  489.  
  490. ;; Validationmem is used by the 740T to map the top 2GB of memory onto the
  491. ;; lower 2GB of memory. This is used during the validation process and must be
  492. ;; provided here as there is no MMU.
  493.  
  494.  
  495. #if ARM740T && Validate
  496. Validationmem=1
  497. #endif
  498.  
  499. ARM810=MMUlator
  500.  
  501. { MMUlator
  502.  
  503. IdleCycles
  504. ;; Uncomment this to have a byte-lane memory interface
  505. ;;Bytelanes
  506. #if Bytelanes
  507. Memory=BytelaneVeneer
  508. #else
  509. Memory=Default
  510. #endif
  511.  
  512. ;; If Track=True, the MMUlator tells you when registers are
  513. ;; written to, etc. Helps debugging.
  514. Track=False
  515.  
  516. ;; Whether to have the "verbose" $statistics
  517. Counters=False
  518.  
  519. { ARM600
  520. CacheWords=4
  521. CacheAssociativity=64
  522. CacheBlocks=4
  523. TLBSize=32
  524. RNG=6
  525. WriteBufferAddrs=2
  526. WriteBufferWords=8
  527. CacheReplaceTicks=1
  528. CacheWrite=WriteThrough
  529. HasUpdateable=True
  530. BufferedSwap=True
  531. Architecture=3
  532. CacheWriteBackInterlock
  533. sNa=Yes
  534. ChipNumber=0x60
  535. Replacement=Random
  536. HasWriteBuffer
  537. HASMMU
  538.  
  539. ARM610:NoCoprocessorInterface
  540. ARM610:ChipNumber=0x61
  541.  
  542. ; Set core/memory clock ratio
  543. MCCFG=2
  544. }
  545.  
  546. ARM610=ARM600
  547.  
  548. { ARM700
  549.  
  550. CacheWords=8
  551. CacheAssociativity=4
  552. CacheBlocks=64
  553. TLBSize=64
  554. RNG=7
  555. WriteBufferAddrs=4
  556. WriteBufferWords=8
  557. CacheReplaceTicks=1
  558. CacheWrite=WriteThrough
  559. HasRFlag
  560. HasUpdateable=False
  561. BufferedSwap=False
  562. Architecture=3
  563. CacheWriteBackInterlock
  564. sNa=Yes
  565. Replacement=Random
  566. Has26BitConfig
  567. HasWriteBuffer
  568. CheckCacheWhenDisabled
  569.  
  570. ChipNumber=0x700
  571.  
  572. ARM710:NoCoprocessorInterface
  573. ARM710:ChipNumber=0x0710
  574. ARM710:Revision=0
  575.  
  576. ARM704:NoCoprocessorInterface
  577. ARM704:CacheWords=4
  578. ARM704:CacheBlocks=64
  579. ARM704:ChipNumber=0x2710
  580. ARM704:Revision=0
  581.  
  582. ARM710a:NoCoprocessorInterface
  583. ARM710a:CacheWords=4
  584. ARM710a:CacheBlocks=128
  585. ARM710a:ChipNumber=0x4710
  586. ARM710a:Revision=0
  587.  
  588. ARM710T:CacheWords=4
  589. ARM710T:CacheAssociativity=4
  590. ARM710T:CacheBlocks=128
  591. ARM710T:Architecture=4T
  592. ARM710T:ChipNumber=0x710
  593. ARM710T:Revision=0
  594. ARM710T:ThumbAware=1
  595. ARM710T:ProcessId=0
  596.  
  597. ARM720T:CacheWords=4
  598. ARM720T:CacheAssociativity=4
  599. ARM720T:CacheBlocks=128
  600. ARM720T:Architecture=4T
  601. ARM720T:ChipNumber=0x720
  602. ARM720T:Revision=0
  603. ARM720T:ThumbAware=1
  604. ARM720T:ProcessId=1
  605. ARM720T:ProcessId
  606.  
  607. ARM740T:CacheWords=4
  608. ARM740T:CacheAssociativity=4
  609. ARM740T:CacheBlocks=128
  610. ARM740T:Architecture=4T
  611. ARM740T:ChipNumber=0x740
  612. ARM740T:Revision=0
  613. ARM740T:ThumbAware=1
  614. ARM740T:ProcessId=0
  615. ARM740T:ProtectionUnit=1
  616. ARM740T:LockDownTLB=0
  617.  
  618. ; Set core/memory clock ratio
  619. MCCFG=3
  620. }
  621.  
  622. ARM710=ARM700
  623. ARM710a=ARM700
  624. ARM704=ARM700
  625. ARM710T=ARM700
  626. ARM720T=ARM700
  627. ARM740T=ARM700
  628.  
  629. { ARM810
  630.  
  631. CacheWords=4
  632. CacheAssociativity=64
  633. CacheBlocks=8
  634. TLBSize=64
  635. RNG=6
  636. WriteBufferAddrs=4
  637. WriteBufferWords=8
  638. CacheReplaceTicks=3
  639. CacheWrite=WriteBack
  640. HasRFlag
  641. NoUpdateable
  642. NoBufferedSwap
  643. Architecture=4
  644. CacheBlockInterlock
  645. ;; If using the PLLs
  646. ;PLLClock
  647. ;RefClkCfg=0
  648. ;PLLCfg=15
  649. ;PLLRange=0
  650. HasBranchPrediction
  651. Replacement=Random
  652. HasWriteBuffer
  653. LockDownCache
  654. LockDownTLB
  655. CheckCacheWhenDisabled
  656.  
  657. ChipNumber=0x810
  658.  
  659. HASMMU
  660.  
  661. ;Set core/memory clock speed ratio
  662. MCCFG=2
  663. }
  664.  
  665. Replacement=rng
  666. WriteBufferWords=8
  667. Revision=0xff
  668.  
  669. ;; Track, if on, displays to the console all CP15 (etc.) operations
  670. Track=Off
  671.  
  672. LRURead
  673. LRUWrite
  674.  
  675. }
  676. #endif
  677.  
  678.  
  679. ;; The "StrongMMU" model provides the cache model for the SA-110
  680.  
  681. #if MEMORY_StrongMMU
  682. SA-110=StrongMMU
  683.  
  684. { StrongMMU
  685.  
  686. #if Validate || UseMapFile==False
  687. Config=Standard
  688. #endif
  689. Config=Enhanced
  690. ChipNumber=0x110
  691.  
  692. ;; Clock speed controlled by three values:
  693. ;; See the SA-110 Technical Reference Manual for details.
  694. CCLK=3.68MHz
  695. CCCFG=0
  696. MCCFG=0
  697.  
  698. HasMMU
  699.  
  700. ;; "ClockSwitching" controls whether "clock switching" is disabled (as on
  701. ;; real silicon) or enabled (to simplify benchmarking) on reset.
  702. ClockSwitching=True
  703.  
  704. ;; To enable useful timings for profiling (etc), the StrongARMulator allows
  705. ;; us to divide what would be the real core clock frequency by a factor. This
  706. ;; "slows down" StrongARM, so we get more emulated time per real time.
  707. Time_Scale_Factor=1
  708.  
  709. Memory=Default
  710. }
  711. #endif
  712.  
  713.  
  714. #if MEMORY_ARM940CacheMPU
  715. ;; The "ARM940CacheMPU" model provides the cache/PU model for the ARM940
  716. ARM940T=ARM940CacheMPU
  717.  
  718. { ARM940CacheMPU
  719.  
  720. ChipNumber=0x940
  721.  
  722. ;;Set the number of cache lines
  723. ICache_Lines=256
  724. DCache_Lines=256
  725. ;; 256 = 4 Kbytes
  726. ;; 512 = 8 Kbytes
  727.  
  728. ;; Clock speed controlled by:
  729. MCCfg=1
  730. HasPU
  731. Memory=Default
  732. }
  733. #endif
  734.  
  735. #if MEMORY_ARM946CacheMPU
  736. ;; The "ARM946CacheMPU" model provides the cache/PU model for the ARM946
  737. ARM946T=ARM946CacheMPU
  738.  
  739. { ARM946CacheMPU
  740.  
  741. ChipNumber=0x946
  742.  
  743. ;;Set the number of cache lines
  744. ICache_Lines=256
  745. DCache_Lines=256
  746. ;; 128 = 4 KBytes DO NOT USE 4KBytes cache size.
  747. ;; 256 = 8 KBytes
  748. ;; 512 = 16 KBytes
  749. ;;1024 = 32 KBytes
  750. ;;2048 = 64 KBytes
  751. ;;4096 = 128 KBytes
  752. ;8192 = 256 KBytes
  753.  
  754. ICache_Associativity=4
  755. DCache_Associativity=4
  756. CacheLineLength=8
  757.  
  758. ;; Clock speed controlled by:
  759. MCCfg=1
  760. HasPU
  761. Memory=Default
  762. }
  763. #endif
  764.  
  765.  
  766.  
  767. #if MEMORY_ARM920CacheMMU
  768. ;; The "ARM920CacheMMU" model provides the cache/MMU model for the ARM920
  769. ARM920T=ARM920CacheMMU
  770.  
  771. { ARM920CacheMMU
  772.  
  773. #if Validate
  774. Config=Standard
  775. #endif
  776. Config=Enhanced
  777. ChipNumber=0x920
  778.  
  779. ;; Clock speed controlled by a pair of values:
  780. CCCfg=0
  781. MCCfg=8
  782. HasMMU
  783. Memory=Default
  784. }
  785. #endif
  786.  
  787.  
  788.  
  789. #if MEMORY_BytelaneVeneer
  790. BytelaneVeneer:Memory=Default
  791. #endif
  792.  
  793. #if MEMORY_MapFile
  794. { MapFile
  795. ;; Options for the mapfile memory model
  796. CountWaitStates=True
  797. AMBABusCounts=False
  798. SpotISCycles=True
  799. ISTiming=Early
  800. }
  801. #endif
  802.  
  803.  
  804. ;; The Switch model is configured just with the address decode for the
  805. ;; main memory model. Other peripherals are added to the configuration
  806. ;; dynamically by ARMul_AddToSwitch.
  807. #if MEMORY_Switch
  808. { Switch
  809. ;; The switch memory model multiplexes peripheral models with a memory
  810. ;; model
  811.  
  812. ;;; Specify Range or Mask to use range or mask decoding.
  813. ;; Decode for the RAM (Memory Model)
  814. ; Use RAM from 0->0x7fffffff
  815. Range=0x0,0x07ffffff
  816.  
  817. ;Use RAM for (address & 0x80000000) == 0
  818. ;Mask=0x80000000,0x0
  819. }
  820. #endif
  821.  
  822.  
  823.  
  824. ;; end of memories
  825. }
  826.  
  827. ;; Co-processor bus
  828. CoprocessorBus=ARMCoprocessorBus
  829.  
  830. ;;
  831. ;; Coprocessor configurations
  832. ;;
  833.  
  834. { Coprocessors
  835.  
  836. ; Here is the list of co-processors, in the form:
  837. ; Coprocessor[<n>]=Name
  838.  
  839. #if COPROCESSOR_DummyMMU
  840. ;; By default, we install a dummy MMU on co-processor 15.
  841. CoProcessor[15]=DummyMMU
  842.  
  843. ; Here is the configuration for the co-processors.
  844.  
  845. ;; The Dummy MMU can be configured to return a given Chip ID
  846. ;DummyMMU:ChipID=
  847. #endif
  848. }
  849.  
  850. ;;
  851. ;; Basic models (ARMulator extensions)
  852. ;;
  853.  
  854. { EarlyModels
  855. ;;
  856. ;; "EarlyModels" get run before memory initialization, "Models" after.
  857. ;;
  858.  
  859. #if MODEL_Watchpoints && WatchpointsEnabled==True
  860. ;; Inserts a watchpoint model into the memory hierarchy.
  861. Watchpoints
  862. #endif
  863.  
  864.  
  865. #if MODEL_Tracer
  866. { Tracer
  867. ;; Output options - can be plaintext to file, binary to file or to RDI log
  868. ;; window. (Checked in the order RDILog, File, BinFile.)
  869. RDILog=False
  870. File=armul.trc
  871. BinFile=armul.trc
  872. ;; Tracer options - what to trace
  873. TraceInstructions=False
  874. TraceRegisters=False
  875. TraceMemory=True
  876. TraceIdle=False
  877. TraceNonAccounted=False
  878. TraceEvents=False
  879. ;; Where to trace memory - if not set, it will trace at the core.
  880. TraceBus=False
  881. ;; Flags - disassemble instructions; start up with tracing enabled;
  882. Disassemble=True
  883. StartOn=False
  884. }
  885. #endif
  886.  
  887.  
  888.  
  889. ;; Reference Peripheral Memory models
  890. #if MODEL_TimerCounter && TimerEnabled==True
  891. { TimerCounter
  892. Range=0x0a800000,0x0a80003f
  893. CLK=20000000
  894. ;; Interrupt controller source bits - 4 and 5 as standard
  895. IntOne=4
  896. IntTwo=5
  897. ;; set Warn to True to enable warnings about invalid register accesses
  898. Warn=False
  899. Waits=1
  900. }
  901. #endif
  902.  
  903. #if MODEL_WatchDog && WDogEnabled==True
  904. { WatchDog
  905. Range=0xb0000000,0xb0000004
  906. KeyValue=0x12345678
  907. WatchPeriod=0x80000
  908. IRQPeriod=3000
  909. IntNumber=16
  910. StartOnReset=True
  911. RunAfterBark=True
  912. ;; set Warn to True to enable warnings about invalid register accesses
  913. Warn=False
  914. Waits=1
  915. }
  916. #endif
  917.  
  918. #if MODEL_Tube && TubeEnabled==True
  919. { Tube
  920. Range=0x0d800020,0x0d800023
  921. }
  922. #endif
  923.  
  924. #if MODEL_InterruptController && IntCEnabled==True
  925. { InterruptController
  926. Range=0x0a000000,0x0a00010c
  927. ;; set Warn to True to enable warnings about invalid register accesses
  928. Warn=False
  929. Waits=1
  930. }
  931. #endif
  932.  
  933. ;; End of EarlyModels
  934. }
  935.  
  936. { Models
  937.  
  938. #if MODEL_Profiler
  939. { Profiler
  940. ;; For example - to profile the PC value when cache misses happen, set:
  941. ;Type=Event
  942. ;Event=0x00010001
  943. ;EventWord=pc
  944. }
  945. #endif
  946.  
  947. #if MODEL_WindowsHourglass
  948. { WindowsHourglass
  949. ;; We can control how regularly we callback the frontend
  950. ;; More often (lower value) means a slower emulator, but
  951. ;; faster response. The default is 8192.
  952. Rate=8192
  953. }
  954. #endif
  955.  
  956. #if MODEL_DebugComms
  957. ;; Debug comms channel model checks if it's on a processor with ICE
  958. ;; The "Rate" parameter governs how often it tries to give data back
  959. ;; to the debugger, so models the real latency of a JTAG-based system.
  960. { DebugComms
  961. Rate=8192
  962. ; Whether RX and TX are wired up to IRQ/interrupt controller
  963. IRQOnCommsChannel=False
  964. ; Interrupt priorities when using an interrupt controller
  965. CommRXIRQNo=2
  966. CommTXIRQNo=3
  967. }
  968. #endif
  969.  
  970.  
  971.  
  972.  
  973. ;;
  974. ;; Validation co-processor
  975. ;;
  976. #if MODEL_ValidateCP && Validate && Validate==CP
  977. ValidateCP
  978. #endif
  979.  
  980. ;;
  981. ;; Operating system definitions - used only for a NEW_OS_INTERFACE build
  982. ;;
  983.  
  984. ;; The default operating-system is Angel
  985. #if MODEL_Angel && !Validate
  986. { Angel
  987.  
  988. ;; Angel configuration
  989.  
  990. ;; SWIs to use for Angel
  991. AngelSWIARM=0x123456
  992. AngelSWIThumb=0xab
  993.  
  994.  
  995. #if PID7T
  996. HeapBase=0x02069000
  997. HeapLimit=0x02079000
  998. StackBase=0x02080000
  999. StackLimit=0x02079000
  1000. #else
  1001. HeapBase=0x0
  1002. HeapLimit=0x07000000
  1003. StackBase=0x08000000
  1004. StackLimit=0x07000000
  1005. #endif
  1006.  
  1007.  
  1008. Demon=Yes
  1009.  
  1010. #if !FPE || Demon==No
  1011. FPE=No
  1012. #endif
  1013.  
  1014. ;; Demon configuration
  1015.  
  1016. ;; Configure the locations of stacks, etc.
  1017. AddrSuperStack=0xa00
  1018. AddrAbortStack=0x800
  1019. AddrUndefStack=0x700
  1020. AddrIRQStack=0x500
  1021. AddrFIQStack=0x400
  1022.  
  1023. ;; The default location of the user mode stack
  1024. AddrUserStack=0x80000
  1025.  
  1026. ;; Start of the "soft vector" code
  1027. AddrSoftVectors=0xa40
  1028.  
  1029. ;; Where to place a copy of the command line
  1030. AddrCmdLine=0xf00
  1031.  
  1032. ;; Address and workspace for installed handlers
  1033. AddrsOfHandlers=0xad0
  1034.  
  1035. ;; Default handlers
  1036. SoftVectorCode=0xb80
  1037. }
  1038. #endif
  1039.  
  1040. #if MODEL_ValidateOS && Validate && Validate==OS
  1041. ValidateOS
  1042. #endif
  1043.  
  1044. #if UsePageTables==True && MODEL_Pagetables && !Validate
  1045. ;; Page tables
  1046. { Pagetables
  1047. MMU=Yes
  1048. AlignFaults=No
  1049. Cache=Yes
  1050. WriteBuffer=Yes
  1051. Prog32=Yes
  1052. Data32=Yes
  1053. LateAbort=Yes
  1054. ;; The following is set to the default setting of the processor core
  1055. ;; (which is controlled from the command-line or configuration window).
  1056. ;; Only uncomment if you wish to override that setting.
  1057. ;BigEnd=
  1058. BranchPredict=Yes
  1059. ICache=Yes
  1060. HighExceptionVectors=No
  1061.  
  1062. ;; Used by the 940 to control the clock mode. Use this flag
  1063. ;; to configure the clock mode for the processor. If FastBus is enabled
  1064. ;; fast bus mode will be used otherwise synchronous mode is used.
  1065.  
  1066. FastBus=No
  1067.  
  1068.  
  1069. PageTableBase=0xa0000000
  1070. DAC=0x00000001
  1071.  
  1072. { Region[0]
  1073. VirtualBase=0
  1074. PhysicalBase=0
  1075. Size=4GB
  1076. Cacheable=No
  1077. Bufferable=No
  1078. Updateable=Yes
  1079. Domain=0
  1080. AccessPermissions=3
  1081. Translate=Yes
  1082. }
  1083.  
  1084. { Region[1]
  1085. VirtualBase=0
  1086. PhysicalBase=0
  1087. Size=128Mb
  1088. Cacheable=Yes
  1089. Bufferable=Yes
  1090. Updateable=Yes
  1091. Domain=0
  1092. AccessPermissions=3
  1093. Translate=Yes
  1094. }
  1095.  
  1096.  
  1097.  
  1098.  
  1099. ;; You can add more "regions" here: Region[1], etc.
  1100.  
  1101.  
  1102.  
  1103.  
  1104. }
  1105. #endif
  1106.  
  1107. ;; The StackUse model continually monitors the stack pointer and
  1108. ;; reports the amount of stack used in $statistics. It needs to be
  1109. ;; configured with the stack's location.
  1110. #if MODEL_StackUse && TrackStack==True
  1111. { StackUse
  1112. StackBase=0x80000000
  1113. StackLimit=0x70000000
  1114. }
  1115. #endif
  1116.  
  1117. }
  1118.  
  1119. ;; EOF armul.cnf

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