TEXT   54

gpu yaml

Guest on 24th July 2022 05:45:34 AM

  1. # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2. %YAML 1.2
  3. ---
  4.  
  5. $id: "http://devicetree.org/schemas/display/msm/gpu.yaml#"
  6. $schema: "http://devicetree.org/meta-schemas/core.yaml#"
  7.  
  8. title: Devicetree bindings for the Adreno or Snapdragon GPUs
  9.  
  10. maintainers:
  11.   - Rob Clark <robdclark@gmail.com>
  12.  
  13. properties:
  14.   compatible:
  15.     oneOf:
  16.       - description: |
  17.           The driver is parsing the compat string for Adreno to
  18.           figure out the gpu-id and patch level.
  19.         items:
  20.           - pattern: '^qcom,adreno-[3-6][0-9][0-9]\.[0-9]$'
  21.           - const: qcom,adreno
  22.       - description: |
  23.           The driver is parsing the compat string for Imageon to
  24.           figure out the gpu-id and patch level.
  25.         items:
  26.           - pattern: '^amd,imageon-200\.[0-1]$'
  27.           - const: amd,imageon
  28.  
  29.   clocks: true
  30.  
  31.   clock-names: true
  32.  
  33.   reg:
  34.     minItems: 1
  35.     maxItems: 3
  36.  
  37.   reg-names:
  38.     minItems: 1
  39.     items:
  40.       - const: kgsl_3d0_reg_memory
  41.       - const: cx_mem
  42.       - const: cx_dbgc
  43.  
  44.   interrupts:
  45.     maxItems: 1
  46.  
  47.   interrupt-names:
  48.     maxItems: 1
  49.  
  50.   interconnects:
  51.     minItems: 1
  52.     maxItems: 2
  53.  
  54.   interconnect-names:
  55.     minItems: 1
  56.     items:
  57.       - const: gfx-mem
  58.       - const: ocmem
  59.  
  60.   iommus:
  61.     maxItems: 1
  62.  
  63.   sram:
  64.     $ref: /schemas/types.yaml#/definitions/phandle-array
  65.     minItems: 1
  66.     maxItems: 4
  67.     items:
  68.       maxItems: 1
  69.     description: |
  70.       phandles to one or more reserved on-chip SRAM regions.
  71.       phandle to the On Chip Memory (OCMEM) that's present on some a3xx and
  72.       a4xx Snapdragon SoCs. See
  73.       Documentation/devicetree/bindings/sram/qcom,ocmem.yaml
  74.  
  75.   operating-points-v2: true
  76.   opp-table:
  77.     type: object
  78.  
  79.   power-domains:
  80.     maxItems: 1
  81.  
  82.   zap-shader:
  83.     type: object
  84.     description: |
  85.       For a5xx and a6xx devices this node contains a memory-region that
  86.       points to reserved memory to store the zap shader that can be used to
  87.       help bring the GPU out of secure mode.
  88.     properties:
  89.       memory-region:
  90.         $ref: /schemas/types.yaml#/definitions/phandle
  91.  
  92.       firmware-name:
  93.         description: |
  94.           Default name of the firmware to load to the remote processor.
  95.  
  96.   "#cooling-cells":
  97.     const: 2
  98.  
  99.   nvmem-cell-names:
  100.     maxItems: 1
  101.  
  102.   nvmem-cells:
  103.     description: efuse registers
  104.     maxItems: 1
  105.  
  106.   qcom,gmu:
  107.     $ref: /schemas/types.yaml#/definitions/phandle
  108.     description: |
  109.       For GMU attached devices a phandle to the GMU device that will
  110.       control the power for the GPU.
  111.  
  112.  
  113. required:
  114.   - compatible
  115.   - reg
  116.   - interrupts
  117.  
  118. additionalProperties: false
  119.  
  120. allOf:
  121.   - if:
  122.       properties:
  123.         compatible:
  124.           contains:
  125.             pattern: '^qcom,adreno-[3-5][0-9][0-9]\.[0-9]$'
  126.  
  127.     then:
  128.       properties:
  129.         clocks:
  130.           minItems: 2
  131.           maxItems: 7
  132.  
  133.         clock-names:
  134.           items:
  135.             anyOf:
  136.               - const: core
  137.                 description: GPU Core clock
  138.               - const: iface
  139.                 description: GPU Interface clock
  140.               - const: mem
  141.                 description: GPU Memory clock
  142.               - const: mem_iface
  143.                 description: GPU Memory Interface clock
  144.               - const: alt_mem_iface
  145.                 description: GPU Alternative Memory Interface clock
  146.               - const: gfx3d
  147.                 description: GPU 3D engine clock
  148.               - const: rbbmtimer
  149.                 description: GPU RBBM Timer for Adreno 5xx series
  150.           minItems: 2
  151.           maxItems: 7
  152.  
  153.       required:
  154.         - clocks
  155.         - clock-names
  156.   - if:
  157.       properties:
  158.         compatible:
  159.           contains:
  160.             pattern: '^qcom,adreno-6[0-9][0-9]\.[0-9]$'
  161.  
  162.     then: # Since Adreno 6xx series clocks should be defined in GMU
  163.       properties:
  164.         clocks: false
  165.         clock-names: false
  166.  
  167. examples:
  168.   - |
  169.  
  170.     // Example a3xx/4xx:
  171.  
  172.     #include <dt-bindings/clock/qcom,mmcc-msm8974.h>
  173.     #include <dt-bindings/clock/qcom,rpmcc.h>
  174.     #include <dt-bindings/interrupt-controller/irq.h>
  175.     #include <dt-bindings/interrupt-controller/arm-gic.h>
  176.  
  177.     gpu: gpu@fdb00000 {
  178.         compatible = "qcom,adreno-330.2", "qcom,adreno";
  179.  
  180.         reg = <0xfdb00000 0x10000>;
  181.         reg-names = "kgsl_3d0_reg_memory";
  182.  
  183.         clock-names = "core", "iface", "mem_iface";
  184.         clocks = <&mmcc OXILI_GFX3D_CLK>,
  185.                  <&mmcc OXILICX_AHB_CLK>,
  186.                  <&mmcc OXILICX_AXI_CLK>;
  187.  
  188.         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
  189.         interrupt-names = "kgsl_3d0_irq";
  190.  
  191.         sram = <&gpu_sram>;
  192.         power-domains = <&mmcc OXILICX_GDSC>;
  193.         operating-points-v2 = <&gpu_opp_table>;
  194.         iommus = <&gpu_iommu 0>;
  195.         #cooling-cells = <2>;
  196.     };
  197.  
  198.     ocmem@fdd00000 {
  199.         compatible = "qcom,msm8974-ocmem";
  200.  
  201.         reg = <0xfdd00000 0x2000>,
  202.               <0xfec00000 0x180000>;
  203.         reg-names = "ctrl", "mem";
  204.  
  205.         clocks = <&rpmcc RPM_SMD_OCMEMGX_CLK>,
  206.                  <&mmcc OCMEMCX_OCMEMNOC_CLK>;
  207.         clock-names = "core", "iface";
  208.  
  209.         #address-cells = <1>;
  210.         #size-cells = <1>;
  211.         ranges = <0 0xfec00000 0x100000>;
  212.  
  213.         gpu_sram: gpu-sram@0 {
  214.             reg = <0x0 0x100000>;
  215.         };
  216.     };
  217.   - |
  218.  
  219.     // Example a6xx (with GMU):
  220.  
  221.     #include <dt-bindings/clock/qcom,gpucc-sdm845.h>
  222.     #include <dt-bindings/clock/qcom,gcc-sdm845.h>
  223.     #include <dt-bindings/power/qcom-rpmpd.h>
  224.     #include <dt-bindings/interrupt-controller/irq.h>
  225.     #include <dt-bindings/interrupt-controller/arm-gic.h>
  226.     #include <dt-bindings/interconnect/qcom,sdm845.h>
  227.  
  228.     reserved-memory {
  229.         #address-cells = <2>;
  230.         #size-cells = <2>;
  231.  
  232.         zap_shader_region: gpu@8f200000 {
  233.             compatible = "shared-dma-pool";
  234.             reg = <0x0 0x90b00000 0x0 0xa00000>;
  235.             no-map;
  236.         };
  237.     };
  238.  
  239.     gpu@5000000 {
  240.         compatible = "qcom,adreno-630.2", "qcom,adreno";
  241.  
  242.         reg = <0x5000000 0x40000>, <0x509e000 0x10>;
  243.         reg-names = "kgsl_3d0_reg_memory", "cx_mem";
  244.  
  245.         #cooling-cells = <2>;
  246.  
  247.         interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
  248.  
  249.         iommus = <&adreno_smmu 0>;
  250.  
  251.         operating-points-v2 = <&gpu_opp_table>;
  252.  
  253.         interconnects = <&rsc_hlos MASTER_GFX3D &rsc_hlos SLAVE_EBI1>;
  254.         interconnect-names = "gfx-mem";
  255.  
  256.         qcom,gmu = <&gmu>;
  257.  
  258.         gpu_opp_table: opp-table {
  259.             compatible = "operating-points-v2";
  260.  
  261.             opp-430000000 {
  262.                 opp-hz = /bits/ 64 <430000000>;
  263.                 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
  264.                 opp-peak-kBps = <5412000>;
  265.             };
  266.  
  267.             opp-355000000 {
  268.                 opp-hz = /bits/ 64 <355000000>;
  269.                 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
  270.                 opp-peak-kBps = <3072000>;
  271.             };
  272.  
  273.             opp-267000000 {
  274.                 opp-hz = /bits/ 64 <267000000>;
  275.                 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
  276.                 opp-peak-kBps = <3072000>;
  277.             };
  278.  
  279.             opp-180000000 {
  280.                 opp-hz = /bits/ 64 <180000000>;
  281.                 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
  282.                 opp-peak-kBps = <1804000>;
  283.             };
  284.         };
  285.  
  286.         zap-shader {
  287.             memory-region = <&zap_shader_region>;
  288.             firmware-name = "qcom/LENOVO/81JL/qcdxkmsuc850.mbn";
  289.         };
  290.     };

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