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aardvark pci
Guest on 22nd August 2022 01:04:11 AM


  1. Aardvark PCIe controller
  2.  
  3. This PCIe controller is used on the Marvell Armada 3700 ARM64 SoC.
  4.  
  5. The Device Tree node describing an Aardvark PCIe controller must
  6. contain the following properties:
  7.  
  8.  - compatible: Should be "marvell,armada-3700-pcie"
  9.  - reg: range of registers for the PCIe controller
  10.  - interrupts: the interrupt line of the PCIe controller
  11.  - #address-cells: set to <3>
  12.  - #size-cells: set to <2>
  13.  - device_type: set to "pci"
  14.  - ranges: ranges for the PCI memory and I/O regions
  15.  - #interrupt-cells: set to <1>
  16.  - msi-controller: indicates that the PCIe controller can itself
  17.    handle MSI interrupts
  18.  - msi-parent: pointer to the MSI controller to be used
  19.  - interrupt-map-mask and interrupt-map: standard PCI properties to
  20.    define the mapping of the PCIe interface to interrupt numbers.
  21.  - bus-range: PCI bus numbers covered
  22.  - phys: the PCIe PHY handle
  23.  - max-link-speed: see pci.txt
  24.  - reset-gpios: see pci.txt
  25.  
  26. In addition, the Device Tree describing an Aardvark PCIe controller
  27. must include a sub-node that describes the legacy interrupt controller
  28. built into the PCIe controller. This sub-node must have the following
  29. properties:
  30.  
  31.  - interrupt-controller
  32.  - #interrupt-cells: set to <1>
  33.  
  34. Example:
  35.  
  36.         pcie0: pcie@d0070000 {
  37.                 compatible = "marvell,armada-3700-pcie";
  38.                 device_type = "pci";
  39.                 reg = <0 0xd0070000 0 0x20000>;
  40.                 #address-cells = <3>;
  41.                 #size-cells = <2>;
  42.                 bus-range = <0x00 0xff>;
  43.                 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
  44.                 #interrupt-cells = <1>;
  45.                 msi-controller;
  46.                 msi-parent = <&pcie0>;
  47.                 ranges = <0x82000000 0 0xe8000000   0 0xe8000000 0 0x1000000 /* Port 0 MEM */
  48.                           0x81000000 0 0xe9000000   0 0xe9000000 0 0x10000>; /* Port 0 IO*/
  49.                 interrupt-map-mask = <0 0 0 7>;
  50.                 interrupt-map = <0 0 0 1 &pcie_intc 0>,
  51.                                 <0 0 0 2 &pcie_intc 1>,
  52.                                 <0 0 0 3 &pcie_intc 2>,
  53.                                 <0 0 0 4 &pcie_intc 3>;
  54.                 phys = <&comphy1 0>;
  55.                 pcie_intc: interrupt-controller {
  56.                         interrupt-controller;
  57.                         #interrupt-cells = <1>;
  58.                 };
  59.         };
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