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cdns cdns-pcie host

Guest on 22nd August 2022 01:17:11 AM

  1. * Cadence PCIe host controller
  2.  
  3. This PCIe controller inherits the base properties defined in
  4. host-generic-pci.txt.
  5.  
  6. Required properties:
  7. - compatible: Should contain "cdns,cdns-pcie-host" to identify the IP used.
  8. - reg: Should contain the controller register base address, PCIe configuration
  9.   window base address, and AXI interface region base address respectively.
  10. - reg-names: Must be "reg", "cfg" and "mem" respectively.
  11. - #address-cells: Set to <3>
  12. - #size-cells: Set to <2>
  13. - device_type: Set to "pci"
  14. - ranges: Ranges for the PCI memory and I/O regions
  15. - #interrupt-cells: Set to <1>
  16. - interrupt-map-mask and interrupt-map: Standard PCI properties to define the
  17.   mapping of the PCIe interface to interrupt numbers.
  18.  
  19. Optional properties:
  20. - cdns,max-outbound-regions: Set to maximum number of outbound regions
  21.   (default 32)
  22. - cdns,no-bar-match-nbits: Set into the no BAR match register to configure the
  23.   number of least significant bits kept during inbound (PCIe -> AXI) address
  24.   translations (default 32)
  25. - vendor-id: The PCI vendor ID (16 bits, default is design dependent)
  26. - device-id: The PCI device ID (16 bits, default is design dependent)
  27. - phys: From PHY bindings: List of Generic PHY phandles. One per lane if more
  28.   than one in the list.  If only one PHY listed it must manage all lanes.
  29. - phy-names:  List of names to identify the PHY.
  30.  
  31. Example:
  32.  
  33. pcie@fb000000 {
  34.         compatible = "cdns,cdns-pcie-host";
  35.         device_type = "pci";
  36.         #address-cells = <3>;
  37.         #size-cells = <2>;
  38.         bus-range = <0x0 0xff>;
  39.         linux,pci-domain = <0>;
  40.         cdns,max-outbound-regions = <16>;
  41.         cdns,no-bar-match-nbits = <32>;
  42.         vendor-id = /bits/ 16 <0x17cd>;
  43.         device-id = /bits/ 16 <0x0200>;
  44.  
  45.         reg = <0x0 0xfb000000  0x0 0x01000000>,
  46.               <0x0 0x41000000  0x0 0x00001000>,
  47.               <0x0 0x40000000  0x0 0x04000000>;
  48.         reg-names = "reg", "cfg", "mem";
  49.  
  50.         ranges = <0x02000000 0x0 0x42000000  0x0 0x42000000  0x0 0x1000000>,
  51.                  <0x01000000 0x0 0x43000000  0x0 0x43000000  0x0 0x0010000>;
  52.  
  53.         #interrupt-cells = <0x1>;
  54.  
  55.         interrupt-map = <0x0 0x0 0x0  0x1  &gic  0x0 0x0 0x0 14 0x1
  56.                          0x0 0x0 0x0  0x2  &gic  0x0 0x0 0x0 15 0x1
  57.                          0x0 0x0 0x0  0x3  &gic  0x0 0x0 0x0 16 0x1
  58.                          0x0 0x0 0x0  0x4  &gic  0x0 0x0 0x0 17 0x1>;
  59.  
  60.         interrupt-map-mask = <0x0 0x0 0x0  0x7>;
  61.  
  62.         msi-parent = <&its_pci>;
  63.  
  64.         phys = <&pcie_phy0>;
  65.         phy-names = "pcie-phy";
  66. };

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