TEXT 15
Cpu.log Guest on 19th September 2020 12:47:16 AM
  1. C:\PROGRAM FILES\EXEMPLAR LOGIC\GALILEO 4.1.1\BIN\WIN32\gc.exe \
  2. C:/perry/ex_cpu/Cpulib.vhd C:/perry/ex_cpu/Alu.vhd C:/perry/ex_cpu/Comp.vhd C:/perry/ex_cpu/Control.vhd C:/perry/ex_cpu/Reg.vhd C:/perry/ex_cpu/Regarray.vhd C:/perry/ex_cpu/Shift.vhd C:/perry/ex_cpu/Trireg.vhd C:/perry/ex_cpu/Cpu.vhd \
  3. C:/perry/ex_cpu/Cpu.edf -input_format=VHDL -target=flex10 -output_format=EDIF \
  4. -area -effort=quick -report_full -encoding=OneHot -wire_tree=Worst -nocontrol \
  5. -vhdl_93 -chip
  6. -------------------------------------------------
  7. Galileo - V4.1.1 (build 1.92, compiled Aug  4 1997 at 21:30:46)
  8. Copyright 1990-1996 Exemplar Logic, Inc.  All rights reserved.
  9.  
  10. Checking Security ...
  11. Info: setting encoding to OneHot
  12. Info: setting wire_tree to Worst
  13. --
  14. -- Welcome to Galileo
  15. -- Run Started On Mon Dec 22 16:04:48 Pacific Daylight Time 1997
  16. --
  17. -- read -format VHDL {C:/perry/ex_cpu/Cpulib.vhd C:/perry/ex_cpu/Alu.vhd C:/perry/ex_cpu/Comp.vhd C:/perry/ex_cpu/Control.vhd C:/perry/ex_cpu/Reg.vhd C:/perry/ex_cpu/Regarray.vhd C:/perry/ex_cpu/Shift.vhd C:/perry/ex_cpu/Trireg.vhd C:/perry/ex_cpu/Cpu.vhd}
  18. -- Reading file C:\PROGRA~1\EXEMPL~1\GALILE~1.1\data\standard.vhd for unit standard
  19. -- Loading package standard into library std
  20. -- Reading vhdl file C:/perry/ex_cpu/Cpulib.vhd into library work
  21. -- Reading file C:\PROGRA~1\EXEMPL~1\GALILE~1.1\data\std_1164.vhd for unit std_logic_1164
  22. -- Loading package std_logic_1164 into library ieee
  23. -- Searching for SYNOPSYS package std_logic_arith..
  24. -- Reading file C:\PROGRA~1\EXEMPL~1\GALILE~1.1\data\syn_arit.vhd for unit std_logic_arith
  25. -- Loading package std_logic_arith into library ieee
  26. "syn_arit.vhd",line 419: Warning, variable z is never assigned a value.
  27. "syn_arit.vhd",line 428: Warning, variable z is never assigned a value.
  28. "syn_arit.vhd",line 437: Warning, variable z is never assigned a value.
  29. "syn_arit.vhd",line 446: Warning, variable z is never assigned a value.
  30. "syn_arit.vhd",line 1341: Warning, variable z is never assigned a value.
  31. "syn_arit.vhd",line 1349: Warning, variable z is never assigned a value.
  32. -- Loading package cpu_lib into library work
  33. -- Reading vhdl file C:/perry/ex_cpu/Alu.vhd into library work
  34. -- Searching for SYNOPSYS package std_logic_unsigned..
  35. -- Reading file C:\PROGRA~1\EXEMPL~1\GALILE~1.1\data\syn_unsi.vhd for unit std_logic_unsigned
  36. -- Loading package std_logic_unsigned into library ieee
  37. -- Loading entity alu into library work
  38. "C:/perry/ex_cpu/Alu.vhd",line 19: Warning, after clause ignored for synthesis.
  39. "C:/perry/ex_cpu/Alu.vhd",line 22: Warning, after clause ignored for synthesis.
  40. "C:/perry/ex_cpu/Alu.vhd",line 25: Warning, after clause ignored for synthesis.
  41. "C:/perry/ex_cpu/Alu.vhd",line 28: Warning, after clause ignored for synthesis.
  42. "C:/perry/ex_cpu/Alu.vhd",line 31: Warning, after clause ignored for synthesis.
  43. "C:/perry/ex_cpu/Alu.vhd",line 34: Warning, after clause ignored for synthesis.
  44. "C:/perry/ex_cpu/Alu.vhd",line 37: Warning, after clause ignored for synthesis.
  45. "C:/perry/ex_cpu/Alu.vhd",line 40: Warning, after clause ignored for synthesis.
  46. "C:/perry/ex_cpu/Alu.vhd",line 43: Warning, after clause ignored for synthesis.
  47. "C:/perry/ex_cpu/Alu.vhd",line 46: Warning, after clause ignored for synthesis.
  48. "C:/perry/ex_cpu/Alu.vhd",line 49: Warning, after clause ignored for synthesis.
  49. -- Loading architecture rtl of alu into library work
  50. -- Reading vhdl file C:/perry/ex_cpu/Comp.vhd into library work
  51. -- Loading entity comp into library work
  52. "C:/perry/ex_cpu/Comp.vhd",line 20: Warning, after clause ignored for synthesis.
  53. "C:/perry/ex_cpu/Comp.vhd",line 22: Warning, after clause ignored for synthesis.
  54. "C:/perry/ex_cpu/Comp.vhd",line 26: Warning, after clause ignored for synthesis.
  55. "C:/perry/ex_cpu/Comp.vhd",line 28: Warning, after clause ignored for synthesis.
  56. "C:/perry/ex_cpu/Comp.vhd",line 32: Warning, after clause ignored for synthesis.
  57. "C:/perry/ex_cpu/Comp.vhd",line 34: Warning, after clause ignored for synthesis.
  58. "C:/perry/ex_cpu/Comp.vhd",line 38: Warning, after clause ignored for synthesis.
  59. "C:/perry/ex_cpu/Comp.vhd",line 40: Warning, after clause ignored for synthesis.
  60. "C:/perry/ex_cpu/Comp.vhd",line 44: Warning, after clause ignored for synthesis.
  61. "C:/perry/ex_cpu/Comp.vhd",line 46: Warning, after clause ignored for synthesis.
  62. "C:/perry/ex_cpu/Comp.vhd",line 50: Warning, after clause ignored for synthesis.
  63. "C:/perry/ex_cpu/Comp.vhd",line 52: Warning, after clause ignored for synthesis.
  64. -- Loading architecture rtl of comp into library work
  65. -- Reading vhdl file C:/perry/ex_cpu/Control.vhd into library work
  66. -- Loading entity control into library work
  67. "C:/perry/ex_cpu/Control.vhd",line 55: Warning, after clause ignored for synthesis.
  68. "C:/perry/ex_cpu/Control.vhd",line 274: Warning, after clause ignored for synthesis.
  69. "C:/perry/ex_cpu/Control.vhd",line 412: Warning, after clause ignored for synthesis.
  70. "C:/perry/ex_cpu/Control.vhd",line 414: Warning, after clause ignored for synthesis.
  71. -- Loading architecture rtl of control into library work
  72. "C:/perry/ex_cpu/Control.vhd",line 14: Warning, output addrregrd is never assigned a value.
  73. -- Reading vhdl file C:/perry/ex_cpu/Reg.vhd into library work
  74. -- Loading entity reg into library work
  75. "C:/perry/ex_cpu/Reg.vhd",line 16: Warning, after clause ignored for synthesis.
  76. -- Loading architecture rtl of reg into library work
  77. -- Reading vhdl file C:/perry/ex_cpu/Regarray.vhd into library work
  78. -- Loading entity regarray into library work
  79. "C:/perry/ex_cpu/Regarray.vhd",line 24: Warning, after clause ignored for synthesis.
  80. "C:/perry/ex_cpu/Regarray.vhd",line 30: Warning, after clause ignored for synthesis.
  81. "C:/perry/ex_cpu/Regarray.vhd",line 32: Warning, after clause ignored for synthesis.
  82. -- Loading architecture rtl of regarray into library work
  83. -- Reading vhdl file C:/perry/ex_cpu/Shift.vhd into library work
  84. -- Loading entity shift into library work
  85. "C:/perry/ex_cpu/Shift.vhd",line 17: Warning, after clause ignored for synthesis.
  86. "C:/perry/ex_cpu/Shift.vhd",line 20: Warning, after clause ignored for synthesis.
  87. "C:/perry/ex_cpu/Shift.vhd",line 23: Warning, after clause ignored for synthesis.
  88. "C:/perry/ex_cpu/Shift.vhd",line 26: Warning, after clause ignored for synthesis.
  89. "C:/perry/ex_cpu/Shift.vhd",line 29: Warning, after clause ignored for synthesis.
  90. -- Loading architecture rtl of shift into library work
  91. -- Reading vhdl file C:/perry/ex_cpu/Trireg.vhd into library work
  92. -- Loading entity trireg into library work
  93. "C:/perry/ex_cpu/Trireg.vhd",line 24: Warning, after clause ignored for synthesis.
  94. "C:/perry/ex_cpu/Trireg.vhd",line 26: Warning, after clause ignored for synthesis.
  95. -- Loading architecture rtl of trireg into library work
  96. -- Reading vhdl file C:/perry/ex_cpu/Cpu.vhd into library work
  97. -- Loading entity cpu into library work
  98. -- Loading architecture rtl of cpu into library work
  99. -- Compiling root entity cpu(rtl)
  100. -- Compiling entity regarray(rtl)
  101. -- Compiling entity trireg(rtl)
  102. "C:/perry/ex_cpu/Trireg.vhd",line 31: Info, conditions are mutually exclusive; resolve without priority.
  103. "C:/perry/ex_cpu/Trireg.vhd",line 31: Warning, else part is never selected for synthesis.
  104. -- Compiling entity alu(rtl)
  105. -- Compiling entity shift(rtl)
  106. -- Compiling entity reg(rtl)
  107. -- Compiling entity comp(rtl)
  108. -- Compiling entity control(rtl)
  109. -- Reading target technology flex10
  110. Reading library file `C:\PROGRA~1\EXEMPL~1\GALILE~1.1\lib\flex10.syn`...
  111. Library version = 0.1
  112. -- Read Module Generators
  113. -- Reading module generator description from file C:\PROGRA~1\EXEMPL~1\GALILE~1.1\data\modgen\flex10.vhd
  114. -- Reading vhdl file C:\PROGRA~1\EXEMPL~1\GALILE~1.1\data\modgen\flex10.vhd into library OPERATORS
  115. -- Modgen File flex10.vhd Version 4.13
  116. -- Pre Optimizing Design .work.cpu.rtl
  117. INFO: Using Ram Cell ram_dq_inclock_16_3_8.
  118. -- Resolving Modgen With modgen_select "small"
  119. -- Start module generator resolving for design .work.cpu.rtl
  120. -- Resolving function add with module generator modgen_add_16_small_false  from file flex10.vhd
  121. -- Resolving function sub with module generator modgen_sub_16_small_false  from file flex10.vhd
  122. -- Resolving function inc with module generator modgen_inc_16_small_false  from file flex10.vhd
  123. -- Resolving function dec with module generator modgen_dec_16_small_false  from file flex10.vhd
  124. -- Resolving function eq with module generator modgen_eq_16_small_false  from file flex10.vhd
  125. -- Resolving function gt with module generator modgen_gt_16_small_false  from file flex10.vhd
  126. -- Resolving function ram_dq with module generator ram_dq_16_3_8_true_false_false  from file flex10.vhd
  127. # ** warning :
  128. FLEX RAMs require address to be registered with inclock for read operation.  Using default implementation.
  129. -- optimize -target flex10 -effort quick -chip -area
  130. -- Start optimization for design .work.cpu.rtl
  131. Info : Tristate at opdata(15) replaced by Buffer.
  132. Info : Tristate at opdata(14) replaced by Buffer.
  133. Info : Tristate at opdata(13) replaced by Buffer.
  134. Info : Tristate at opdata(12) replaced by Buffer.
  135. Info : Tristate at opdata(11) replaced by Buffer.
  136. Info : Tristate at opdata(10) replaced by Buffer.
  137. Info : Tristate at opdata(9) replaced by Buffer.
  138. Info : Tristate at opdata(8) replaced by Buffer.
  139. Info : Tristate at opdata(7) replaced by Buffer.
  140. Info : Tristate at opdata(6) replaced by Buffer.
  141. Info : Tristate at opdata(5) replaced by Buffer.
  142. Info : Tristate at opdata(4) replaced by Buffer.
  143. Info : Tristate at opdata(3) replaced by Buffer.
  144. Info : Tristate at opdata(2) replaced by Buffer.
  145. Info : Tristate at opdata(1) replaced by Buffer.
  146. Info : Tristate at opdata(0) replaced by Buffer.
  147.               est est                                
  148.       Pass    LCs Delay DFFs TRIs  PIs POs    --CPU--
  149.                                                 min:sec
  150.       1       464     46  251   16    3  34      01:11
  151.  
  152. *******************************************************
  153.  
  154. Cell: cpu    View: rtl    Library: work
  155.  
  156. *******************************************************
  157.  
  158.  Number of ports :                      37
  159.  Number of nets :                      853
  160.  Number of instances :                 850
  161.  Number of references to this view :     0
  162.  
  163. Total accumulated area :
  164.  Number of LCs :                       464
  165.  Number of DFFs :                      251
  166.  Number of TRIs :                       16
  167.  Number of CARRYs :                     30
  168.  Number of CASCADEs :                  100
  169.  
  170. -- Start LUT decomposition for design .work.cpu.rtl
  171. -- Writing file C:/perry/ex_cpu/Cpu.edf
  172. -- CPU time taken for this run was 150.93 sec
  173. -- Run ended On Mon September 19 16:07:16 Pacific Daylight Time
  174. -- Galileo run successfully completed.  Goodbye !

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