TEXT 50
Boot.txt Guest on 17th May 2020 09:44:10 AM
  1. ;@Id: boot.tpl#895 @
  2. ;=============================================================================
  3. ;  FILENAME:   boot.asm
  4. ;  Version:    4.18
  5. ;
  6. ;  DESCRIPTION:
  7. ;  M8C Boot Code for CY8C29xxx microcontroller family.
  8. ;
  9. ;  Copyright (c) Cypress Semiconductor 2009. All Rights Reserved.
  10. ;
  11. ; NOTES:
  12. ; PSoC Designer's Device Editor uses a template file, BOOT.TPL, located in
  13. ; the project's root directory to create BOOT.ASM. Any changes made to
  14. ; BOOT.ASM will be  overwritten every time the project is generated; therefore
  15. ; changes should be made to BOOT.TPL not BOOT.ASM. Care must be taken when
  16. ; modifying BOOT.TPL so that replacement strings (such as @PROJECT_NAME)
  17. ; are not accidentally modified.
  18. ;
  19. ;=============================================================================
  20.  
  21. include ".\lib\GlobalParams.inc"        ;File generated by PSoC Designer (Project dependent)
  22. include "m8c.inc"                       ;Part specific file
  23. include "m8ssc.inc"                     ;Part specific file
  24. include "memory.inc"                    ;File generated by PSoC Designer (Project dependent)
  25.  
  26. ;--------------------------------------
  27. ; Export Declarations
  28. ;--------------------------------------
  29.  
  30. export __Start
  31. IF      (TOOLCHAIN & HITECH)
  32. ELSE
  33. export __bss_start
  34. export __data_start
  35. export __idata_start
  36. export __func_lit_start
  37. export __text_start
  38. ENDIF
  39. export  _bGetPowerSetting
  40. export   bGetPowerSetting
  41.  
  42.  
  43. ;--------------------------------------
  44. ; Optimization flags
  45. ;--------------------------------------
  46. ;
  47. ; To change the value of these flags, modify the file boot.tpl, not
  48. ; boot.asm. See the notes in the banner comment at the beginning of
  49. ; this file.
  50.  
  51. ; Optimization for Assembly language (only) projects and C-language projects
  52. ; that do not depend on the C compiler to initialize the values of RAM variables.
  53. ;   Set to 1: Support for C Run-time Environment initialization
  54. ;   Set to 0: Support for C not included. Faster start up, smaller code space.
  55. ;
  56. IF      (TOOLCHAIN & HITECH)
  57. ; The C compiler will customize the startup code - it's not required here
  58.  
  59. C_LANGUAGE_SUPPORT:              equ 0
  60. ELSE
  61. C_LANGUAGE_SUPPORT:              equ 1
  62. ENDIF
  63.  
  64.  
  65. ; The following equate is required for proper operation. Reseting its value
  66. ; is discouraged.  WAIT_FOR_32K is effective only if the crystal oscillator is
  67. ; selected.  If the designer chooses to not wait then stabilization of the ECO
  68. ; and PLL_Lock must take place within user code. See the family data sheet for
  69. ; the requirements of starting the ECO and PLL lock mode.
  70. ;
  71. ;   Set to 1: Wait for XTAL (& PLL if selected) to stabilize before
  72. ;                invoking main
  73. ;   Set to 0: Boot code does not wait; clock may not have stabilized by
  74. ;               the time code in main starts executing.
  75. ;
  76. WAIT_FOR_32K:                    equ 1
  77.  
  78.  
  79. ; For historical reasons, by default the boot code uses an lcall instruction
  80. ; to invoke the user's _main code. If _main executes a return instruction,
  81. ; boot provides an infinite loop. By changing the following equate from zero
  82. ; to 1, boot's lcall will be replaced by a ljmp instruction, saving two
  83. ; bytes on the stack which are otherwise required for the return address. If
  84. ; this option is enabled, _main must not return. (Beginning with the 4.2
  85. ; release, the C compiler automatically places an infinite loop at the end
  86. ; of main, rather than a return instruction.)
  87. ;
  88. ENABLE_LJMP_TO_MAIN:             equ 0
  89.  
  90.  
  91. ;-----------------------------------------------------------------------------
  92. ; Interrupt Vector Table
  93. ;-----------------------------------------------------------------------------
  94. ;
  95. ; Interrupt vector table entries are 4 bytes long.  Each one contains
  96. ; a jump instruction to an ISR (Interrupt Service Routine), although
  97. ; very short ISRs could be encoded within the table itself. Normally,
  98. ; vector jump targets are modified automatically according to the user
  99. ; modules selected. This occurs when the 'Generate Application' opera-
  100. ; tion is run causing PSoC Designer to create boot.asm and the other
  101. ; configuration files. If you need to hard code a vector, update the
  102. ; file boot.tpl, not boot.asm. See the banner comment at the beginning
  103. ; of this file.
  104. ;-----------------------------------------------------------------------------
  105.  
  106.     AREA TOP (ROM, ABS, CON)
  107.  
  108.     org   0                        ;Reset Interrupt Vector
  109. IF      (TOOLCHAIN & HITECH)
  110. ;   jmp   __Start                  ;C compiler fills in this vector
  111. ELSE
  112.     jmp   __Start                  ;First instruction executed following a Reset
  113. ENDIF
  114.  
  115.     org   04h                      ;Low Voltage Detect (LVD) Interrupt Vector
  116.     halt                           ;Stop execution if power falls too low
  117.  
  118.     org   08h                      ;Analog Column 0 Interrupt Vector
  119.     `@INTERRUPT_2`
  120.     reti
  121.  
  122.     org   0Ch                      ;Analog Column 1 Interrupt Vector
  123.     `@INTERRUPT_3`
  124.     reti
  125.  
  126.     org   10h                      ;Analog Column 2 Interrupt Vector
  127.     `@INTERRUPT_4`
  128.     reti
  129.  
  130.     org   14h                      ;Analog Column 3 Interrupt Vector
  131.     `@INTERRUPT_5`
  132.     reti
  133.  
  134.     org   18h                      ;VC3 Interrupt Vector
  135.     `@INTERRUPT_6`
  136.     reti
  137.  
  138.     org   1Ch                      ;GPIO Interrupt Vector
  139.     `@INTERRUPT_7`
  140.     reti
  141.  
  142.     org   20h                      ;PSoC Block DBB00 Interrupt Vector
  143.     ljmp _String1ISR
  144.     reti
  145.  
  146.     org   24h                      ;PSoC Block DBB01 Interrupt Vector
  147.     ljmp _String2ISR
  148.     reti
  149.  
  150.     org   28h                      ;PSoC Block DCB02 Interrupt Vector
  151.     ljmp _String3ISR
  152.     reti
  153.  
  154.     org   2Ch                      ;PSoC Block DCB03 Interrupt Vector
  155.     ljmp _String4ISR
  156.     reti
  157.  
  158.     org   30h                      ;PSoC Block DBB10 Interrupt Vector
  159.     ljmp _String5ISR
  160.     reti
  161.  
  162.     org   34h                      ;PSoC Block DBB11 Interrupt Vector
  163.     ljmp _String6ISR
  164.     reti
  165.  
  166.     org   38h                      ;PSoC Block DCB12 Interrupt Vector
  167.     ljmp _String7ISR
  168.     reti
  169.  
  170.     org   3Ch                      ;PSoC Block DCB13 Interrupt Vector
  171.     ljmp _String8ISR
  172.     reti
  173.  
  174.     org   40h                      ;PSoC Block DBB20 Interrupt Vector
  175.     ljmp _SustainTimerISR
  176.     reti
  177.  
  178.     org   44h                      ;PSoC Block DBB21 Interrupt Vector
  179.     `@INTERRUPT_17`
  180.     reti
  181.  
  182.     org   48h                      ;PSoC Block DCB22 Interrupt Vector
  183.     `@INTERRUPT_18`
  184.     reti
  185.  
  186.     org   4Ch                      ;PSoC Block DCB23 Interrupt Vector
  187.     `@INTERRUPT_19`
  188.     reti
  189.  
  190.     org   50h                      ;PSoC Block DBB30 Interrupt Vector
  191.     `@INTERRUPT_20`
  192.     reti
  193.  
  194.     org   54h                      ;PSoC Block DBB31 Interrupt Vector
  195.     `@INTERRUPT_21`
  196.     reti
  197.  
  198.     org   58h                      ;PSoC Block DCB32 Interrupt Vector
  199.     `@INTERRUPT_22`
  200.     reti
  201.  
  202.     org   5Ch                      ;PSoC Block DCB33 Interrupt Vector
  203.     `@INTERRUPT_23`
  204.     reti
  205.  
  206.     org   60h                      ;PSoC I2C Interrupt Vector
  207.     `@INTERRUPT_24`
  208.     reti
  209.  
  210.     org   64h                      ;Sleep Timer Interrupt Vector
  211.     `@INTERRUPT_25`
  212.     reti
  213.  
  214. ;-----------------------------------------------------------------------------
  215. ;  Start of Execution.
  216. ;-----------------------------------------------------------------------------
  217. ;  The Supervisory ROM SWBootReset function has already completed the
  218. ;  calibrate1 process, loading trim values for 5 volt operation.
  219. ;
  220.  
  221. IF      (TOOLCHAIN & HITECH)
  222.         AREA PD_startup(CODE, REL, CON)
  223. ELSE
  224.     org 68h
  225. ENDIF
  226. __Start:
  227.  
  228.     ; initialize SMP values for voltage stabilization, if required,
  229.     ; leaving power-on reset (POR) level at the default (low) level, at
  230.     ; least for now.
  231.     ;
  232.     M8C_SetBank1
  233.     mov reg[0FAh], 0                            ;Reset flash location
  234.     mov   reg[VLT_CR], SWITCH_MODE_PUMP_JUST | LVD_TBEN_JUST | TRIP_VOLTAGE_JUST
  235.     M8C_SetBank0
  236.  
  237.     ; %53%20%46%46% Apply Erratum 001-05137 workaround
  238.     mov   A, 20h
  239.     romx
  240.     mov   A, 40h
  241.     romx
  242.     mov   A, 60h
  243.     romx
  244.     ; %45%20%46%46% End workaround
  245.  
  246. IF ( WATCHDOG_ENABLE )             ; WDT selected in Global Params
  247.     M8C_EnableWatchDog
  248. ENDIF
  249.  
  250. IF ( SELECT_32K )
  251.     or   reg[CPU_SCR1],  CPU_SCR1_ECO_ALLOWED  ; ECO will be used in this project
  252. ELSE
  253.     and  reg[CPU_SCR1], ~CPU_SCR1_ECO_ALLOWED  ; Prevent ECO from being enabled
  254. ENDIF
  255.  
  256.     ;---------------------------
  257.     ; Set up the Temporary stack
  258.     ;---------------------------
  259.     ; A temporary stack is set up for the SSC instructions.
  260.     ; The real stack start will be assigned later.
  261.     ;
  262. _stack_start:          equ 80h
  263.     mov   A, _stack_start          ; Set top of stack to end of used RAM
  264.     swap  SP, A                    ; This is only temporary if going to LMM
  265.  
  266.     ;-----------------------------------------------
  267.     ; Set Power-related Trim & the AGND Bypass bit.
  268.     ;-----------------------------------------------
  269.  
  270. IF ( POWER_SETTING & POWER_SET_5V0)            ; *** 5.0 Volt operation   ***
  271.  IF ( POWER_SETTING & POWER_SET_SLOW_IMO)      ; *** 6MHZ Main Oscillator ***
  272.     or  reg[CPU_SCR1], CPU_SCR1_SLIMO
  273.     M8SSC_Set2TableTrims 2, SSCTBL2_TRIM_IMO_5V_6MHZ, 1, SSCTBL1_TRIM_BGR_5V, AGND_BYPASS_JUST
  274.  ELSE                                          ; *** 12MHZ Main Oscillator ***
  275.   IF ( AGND_BYPASS )
  276.     ;- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
  277.     ; The 5V trim has already been set, but we need to update the AGNDBYP
  278.     ; bit in the write-only BDG_TR register. Recalculate the register
  279.     ; value using the proper trim values.
  280.     ;- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
  281.     M8SSC_SetTableVoltageTrim 1, SSCTBL1_TRIM_BGR_5V, AGND_BYPASS_JUST
  282.   ENDIF
  283.  ENDIF
  284. ENDIF ; 5.0 V Operation
  285.  
  286. IF ( POWER_SETTING & POWER_SET_3V3)            ; *** 3.3 Volt operation   ***
  287.  IF ( POWER_SETTING & POWER_SET_SLOW_IMO)      ; *** 6MHZ Main Oscillator ***
  288.     or  reg[CPU_SCR1], CPU_SCR1_SLIMO
  289.     M8SSC_Set2TableTrims 2, SSCTBL2_TRIM_IMO_3V_6MHZ, 1, SSCTBL1_TRIM_BGR_3V, AGND_BYPASS_JUST
  290.  ELSE                                          ; *** 12MHZ Main Oscillator ***
  291.     M8SSC_SetTableTrims  1, SSCTBL1_TRIM_IMO_3V_24MHZ, SSCTBL1_TRIM_BGR_3V, AGND_BYPASS_JUST
  292.  ENDIF
  293. ENDIF ; 3.3 Volt Operation
  294.  
  295.     mov  [bSSC_KEY1],  0           ; Lock out Flash and Supervisiory operations
  296.     mov  [bSSC_KEYSP], 0
  297.  
  298.     ;---------------------------------------
  299.     ; Initialize Crystal Oscillator and PLL
  300.     ;---------------------------------------
  301.  
  302. IF ( SELECT_32K & WAIT_FOR_32K )
  303.     ; If the user has requested the External Crystal Oscillator (ECO) then turn it
  304.     ; on and wait for it to stabilize and the system to switch over to it. The PLL
  305.     ; is left off. Set the SleepTimer period is set to 1 sec to time the wait for
  306.     ; the ECO to stabilize.
  307.     ;
  308.     M8C_SetBank1
  309.     mov   reg[OSC_CR0], (SELECT_32K_JUST | OSC_CR0_SLEEP_1Hz | OSC_CR0_CPU_12MHz)
  310.     M8C_SetBank0
  311.     M8C_ClearWDTAndSleep                  ; Reset the sleep timer to get a full second
  312.     or    reg[INT_MSK0], INT_MSK0_SLEEP   ; Enable latching of SleepTimer interrupt
  313.     mov   reg[INT_VC],   0                ; Clear all pending interrupts
  314. .WaitFor1s:
  315.     tst   reg[INT_CLR0], INT_MSK0_SLEEP   ; Test the SleepTimer Interrupt Status
  316.     jz   .WaitFor1s                       ; Interrupt will latch but will not dispatch
  317.                                           ;   since interrupts are not globally enabled
  318. ELSE ; !( SELECT_32K & WAIT_FOR_32K )
  319.     ; Either no ECO, or waiting for stable clock is to be done in main
  320.     M8C_SetBank1
  321.     mov   reg[OSC_CR0], (SELECT_32K_JUST | PLL_MODE_JUST | SLEEP_TIMER_JUST | OSC_CR0_CPU_12MHz)
  322.     M8C_SetBank0
  323.     M8C_ClearWDTAndSleep           ; Reset the watch dog
  324.  
  325. ENDIF ;( SELECT_32K & WAIT_FOR_32K )
  326.  
  327. IF ( PLL_MODE )
  328.     ; Crystal is now fully operational (assuming WAIT_FOR_32K was enabled).
  329.     ; Now start up PLL if selected, and wait 16 msec for it to stabilize.
  330.     ;
  331.     M8C_SetBank1
  332.     mov   reg[OSC_CR0], (SELECT_32K_JUST | PLL_MODE_JUST | OSC_CR0_SLEEP_64Hz | OSC_CR0_CPU_3MHz)
  333.     M8C_SetBank0
  334.     M8C_ClearWDTAndSleep                  ; Reset the sleep timer to get full period
  335.     mov   reg[INT_VC], 0                  ; Clear all pending interrupts
  336.  
  337. .WaitFor16ms:
  338.     tst   reg[INT_CLR0],INT_MSK0_SLEEP    ; Test the SleepTimer Interrupt Status
  339.     jz   .WaitFor16ms
  340.     M8C_SetBank1                          ; continue boot at CPU Speed of SYSCLK/2
  341.     mov   reg[OSC_CR0], (SELECT_32K_JUST | PLL_MODE_JUST | OSC_CR0_SLEEP_64Hz | OSC_CR0_CPU_12MHz)
  342.     M8C_SetBank0
  343.  
  344. IF      ( WAIT_FOR_32K )
  345. ELSE ; !( WAIT_FOR_32K )
  346.     ; Option settings (PLL-Yes, ECO-No) are incompatible - force a syntax error
  347.     ERROR_PSoC Disabling WAIT_FOR_32K requires that the PLL_Lock must be enabled in user code.
  348. ENDIF ;(WAIT_FOR_32K)
  349. ENDIF ;(PLL_MODE)
  350.  
  351.     ;------------------------
  352.     ; Close CT leakage path.
  353.     ;------------------------
  354.     mov   reg[ACB00CR0], 05h
  355.     mov   reg[ACB01CR0], 05h
  356.     mov   reg[ACB02CR0], 05h
  357.     mov   reg[ACB03CR0], 05h
  358.  
  359.  
  360. IF      (TOOLCHAIN & HITECH)
  361.     ;---------------------------------------------
  362.     ; HI-TECH initialization: Enter the Large Memory Model, if applicable
  363.     ;---------------------------------------------
  364.         global          __Lstackps
  365.         mov     a,low __Lstackps
  366.         swap    a,sp
  367.  
  368. IF ( SYSTEM_LARGE_MEMORY_MODEL )
  369.     RAM_SETPAGE_STK SYSTEM_STACK_PAGE      ; relocate stack page ...
  370.     RAM_SETPAGE_IDX2STK            ; initialize other page pointers
  371.     RAM_SETPAGE_CUR 0
  372.     RAM_SETPAGE_MVW 0
  373.     RAM_SETPAGE_MVR 0
  374.     IF ( SYSTEM_IDXPG_TRACKS_STK_PP ); Now enable paging:
  375.     or    F, FLAG_PGMODE_11b       ; LMM w/ IndexPage<==>StackPage
  376.     ELSE
  377.     or    F, FLAG_PGMODE_10b       ; LMM w/ independent IndexPage
  378.     ENDIF ;  SYSTEM_IDXPG_TRACKS_STK_PP
  379. ENDIF ;  SYSTEM_LARGE_MEMORY_MODEL
  380. ELSE
  381.     ;---------------------------------------------
  382.     ; ImageCraft Enter the Large Memory Model, if applicable
  383.     ;---------------------------------------------
  384. IF ( SYSTEM_LARGE_MEMORY_MODEL )
  385.     RAM_SETPAGE_STK SYSTEM_STACK_PAGE      ; relocate stack page ...
  386.     mov   A, SYSTEM_STACK_BASE_ADDR        ;   and offset, if any
  387.     swap  A, SP
  388.     RAM_SETPAGE_IDX2STK            ; initialize other page pointers
  389.     RAM_SETPAGE_CUR 0
  390.     RAM_SETPAGE_MVW 0
  391.     RAM_SETPAGE_MVR 0
  392.  
  393.   IF ( SYSTEM_IDXPG_TRACKS_STK_PP ); Now enable paging:
  394.     or    F, FLAG_PGMODE_11b       ; LMM w/ IndexPage<==>StackPage
  395.   ELSE
  396.     or    F, FLAG_PGMODE_10b       ; LMM w/ independent IndexPage
  397.   ENDIF ;  SYSTEM_IDXPG_TRACKS_STK_PP
  398. ELSE
  399.     mov   A, __ramareas_end        ; Set top of stack to end of used RAM
  400.     swap  SP, A
  401. ENDIF ;  SYSTEM_LARGE_MEMORY_MODEL
  402. ENDIF ; TOOLCHAIN
  403.  
  404.     ;-------------------------
  405.     ; Load Base Configuration
  406.     ;-------------------------
  407.     ; Load global parameter settings and load the user modules in the
  408.     ; base configuration. Exceptions: (1) Leave CPU Speed fast as possible
  409.     ; to minimize start up time; (2) We may still need to play with the
  410.     ; Sleep Timer.
  411.     ;
  412.     lcall LoadConfigInit
  413.  
  414.     ;-----------------------------------
  415.     ; Initialize C Run-Time Environment
  416.     ;-----------------------------------
  417. IF ( C_LANGUAGE_SUPPORT )
  418. IF ( SYSTEM_SMALL_MEMORY_MODEL )
  419.     mov  A,0                           ; clear the 'bss' segment to zero
  420.     mov  [__r0],<__bss_start
  421. BssLoop:
  422.     cmp  [__r0],<__bss_end
  423.     jz   BssDone
  424.     mvi  [__r0],A
  425.     jmp  BssLoop
  426. BssDone:
  427.     mov  A,>__idata_start              ; copy idata to data segment
  428.     mov  X,<__idata_start
  429.     mov  [__r0],<__data_start
  430. IDataLoop:
  431.     cmp  [__r0],<__data_end
  432.     jz   C_RTE_Done
  433.     push A
  434.     romx
  435.     mvi  [__r0],A
  436.     pop  A
  437.     inc  X
  438.     adc  A,0
  439.     jmp  IDataLoop
  440.  
  441. ENDIF ; SYSTEM_SMALL_MEMORY_MODEL
  442.  
  443. IF ( SYSTEM_LARGE_MEMORY_MODEL )
  444.     mov   reg[CUR_PP], >__r0           ; force direct addr mode instructions
  445.                                        ; to use the Virtual Register page.
  446.  
  447.     ; Dereference the constant (flash) pointer pXIData to access the start
  448.     ; of the extended idata area, "xidata." Xidata follows the end of the
  449.     ; text segment and may have been relocated by the Code Compressor.
  450.     ;
  451.     mov   A, >__pXIData                ; Get the address of the flash
  452.     mov   X, <__pXIData                ;   pointer to the xidata area.
  453.     push  A
  454.     romx                               ; get the MSB of xidata's address
  455.     mov   [__r0], A
  456.     pop   A
  457.     inc   X
  458.     adc   A, 0
  459.     romx                               ; get the LSB of xidata's address
  460.     swap  A, X
  461.     mov   A, [__r0]                    ; pXIData (in [A,X]) points to the
  462.                                        ;   XIData structure list in flash
  463.     jmp   .AccessStruct
  464.  
  465.     ; Unpack one element in the xidata "structure list" that specifies the
  466.     ; values of C variables. Each structure contains 3 member elements.
  467.     ; The first is a pointer to a contiguous block of RAM to be initial-
  468.     ; ized. Blocks are always 255 bytes or less in length and never cross
  469.     ; RAM page boundaries. The list terminates when the MSB of the pointer
  470.     ; contains 0xFF. There are two formats for the struct depending on the
  471.     ; value in the second member element, an unsigned byte:
  472.     ; (1) If the value of the second element is non-zero, it represents
  473.     ; the 'size' of the block of RAM to be initialized. In this case, the
  474.     ; third member of the struct is an array of bytes of length 'size' and
  475.     ; the bytes are copied to the block of RAM.
  476.     ; (2) If the value of the second element is zero, the block of RAM is
  477.     ; to be cleared to zero. In this case, the third member of the struct
  478.     ; is an unsigned byte containing the number of bytes to clear.
  479.  
  480. .AccessNextStructLoop:
  481.     inc   X                            ; pXIData++
  482.     adc   A, 0
  483. .AccessStruct:                         ; Entry point for first block
  484.     ;
  485.     ; Assert: pXIData in [A,X] points to the beginning of an XIData struct.
  486.     ;
  487.     M8C_ClearWDT                       ; Clear the watchdog for long inits
  488.     push  A
  489.     romx                               ; MSB of RAM addr (CPU.A <- *pXIData)
  490.     mov   reg[MVW_PP], A               ;   for use with MVI write operations
  491.     inc   A                            ; End of Struct List? (MSB==0xFF?)
  492.     jz    .C_RTE_WrapUp                ;   Yes, C runtime environment complete
  493.     pop   A                            ; restore pXIData to [A,X]
  494.     inc   X                            ; pXIData++
  495.     adc   A, 0
  496.     push  A
  497.     romx                               ; LSB of RAM addr (CPU.A <- *pXIData)
  498.     mov   [__r0], A                    ; RAM Addr now in [reg[MVW_PP],[__r0]]
  499.     pop   A                            ; restore pXIData to [A,X]
  500.     inc   X                            ; pXIData++ (point to size)
  501.     adc   A, 0
  502.     push  A
  503.     romx                               ; Get the size (CPU.A <- *pXIData)
  504.     jz    .ClearRAMBlockToZero         ; If Size==0, then go clear RAM
  505.     mov   [__r1], A                    ;             else downcount in __r1
  506.     pop   A                            ; restore pXIData to [A,X]
  507.  
  508. .CopyNextByteLoop:
  509.     ; For each byte in the structure's array member, copy from flash to RAM.
  510.     ; Assert: pXIData in [A,X] points to previous byte of flash source;
  511.     ;         [reg[MVW_PP],[__r0]] points to next RAM destination;
  512.     ;         __r1 holds a non-zero count of the number of bytes remaining.
  513.     ;
  514.     inc   X                            ; pXIData++ (point to next data byte)
  515.     adc   A, 0
  516.     push  A
  517.     romx                               ; Get the data value (CPU.A <- *pXIData)
  518.     mvi   [__r0], A                    ; Transfer the data to RAM
  519.     tst   [__r0], 0xff                 ; Check for page crossing
  520.     jnz   .CopyLoopTail                ;   No crossing, keep going
  521.     mov   A, reg[ MVW_PP]              ;   If crossing, bump MVW page reg
  522.     inc   A
  523.     mov   reg[ MVW_PP], A
  524. .CopyLoopTail:
  525.     pop   A                            ; restore pXIData to [A,X]
  526.     dec   [__r1]                       ; End of this array in flash?
  527.     jnz   .CopyNextByteLoop            ;   No,  more bytes to copy
  528.     jmp   .AccessNextStructLoop        ;   Yes, initialize another RAM block
  529.  
  530. .ClearRAMBlockToZero:
  531.     pop   A                            ; restore pXIData to [A,X]
  532.     inc   X                            ; pXIData++ (point to next data byte)
  533.     adc   A, 0
  534.     push  A
  535.     romx                               ; Get the run length (CPU.A <- *pXIData)
  536.     mov   [__r1], A                    ; Initialize downcounter
  537.     mov   A, 0                         ; Initialize source data
  538.  
  539. .ClearRAMBlockLoop:
  540.     ; Assert: [reg[MVW_PP],[__r0]] points to next RAM destination and
  541.     ;         __r1 holds a non-zero count of the number of bytes remaining.
  542.     ;
  543.     mvi   [__r0], A                    ; Clear a byte
  544.     tst   [__r0], 0xff                 ; Check for page crossing
  545.     jnz   .ClearLoopTail               ;   No crossing, keep going
  546.     mov   A, reg[ MVW_PP]              ;   If crossing, bump MVW page reg
  547.     inc   A
  548.     mov   reg[ MVW_PP], A
  549.     mov   A, 0                         ; Restore the zero used for clearing
  550. .ClearLoopTail:
  551.     dec   [__r1]                       ; Was this the last byte?
  552.     jnz   .ClearRAMBlockLoop           ;   No,  continue
  553.     pop   A                            ;   Yes, restore pXIData to [A,X] and
  554.     jmp   .AccessNextStructLoop        ;        initialize another RAM block
  555.  
  556. .C_RTE_WrapUp:
  557.     pop   A                            ; balance stack
  558.  
  559. ENDIF ; SYSTEM_LARGE_MEMORY_MODEL
  560.  
  561. C_RTE_Done:
  562.  
  563. ENDIF ; C_LANGUAGE_SUPPORT
  564.  
  565.     ;-------------------------------
  566.     ; Voltage Stabilization for SMP
  567.     ;-------------------------------
  568.  
  569. IF ( POWER_SETTING & POWER_SET_5V0)    ; 5.0V Operation
  570. IF ( SWITCH_MODE_PUMP ^ 1 )            ; SMP is operational
  571.     ;- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
  572.     ; When using the SMP at 5V, we must wait for Vdd to slew from 3.1V to
  573.     ; 5V before enabling the Precision Power-On Reset (PPOR).
  574.     ;- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
  575.     or   reg[INT_MSK0],INT_MSK0_SLEEP
  576.     M8C_SetBank1
  577.     and   reg[OSC_CR0], ~OSC_CR0_SLEEP
  578.     or    reg[OSC_CR0],  OSC_CR0_SLEEP_512Hz
  579.     M8C_SetBank0
  580.     M8C_ClearWDTAndSleep                   ; Restart the sleep timer
  581.     mov   reg[INT_VC], 0                   ; Clear all pending interrupts
  582. .WaitFor2ms:
  583.     tst   reg[INT_CLR0], INT_MSK0_SLEEP    ; Test the SleepTimer Interrupt Status
  584.     jz   .WaitFor2ms                       ; Branch fails when 2 msec has passed
  585. ENDIF ; SMP is operational
  586. ENDIF ; 5.0V Operation
  587.  
  588.     ;-------------------------------
  589.     ; Set Power-On Reset (POR) Level
  590.     ;-------------------------------
  591.  
  592.     ;  The writes to the VLT_CR register below include setting the POR to VLT_CR_POR_HIGH,
  593.     ;  VLT_CR_POR_MID or VLT_CR_POR_LOW. Correctly setting this value is critical to the proper
  594.     ;  operation of the PSoC. The POR protects the M8C from mis-executing when Vdd falls low. These
  595.     ;  values should not be changed from the settings here. Failure to follow this instruction could
  596.     ;  lead to corruption of PSoC flash.
  597.  
  598.     M8C_SetBank1
  599.  
  600. IF (POWER_SETTING & POWER_SET_5V0)          ; 5.0V Operation?
  601.  IF (POWER_SETTING & POWER_SET_SLOW_IMO)    ; and Slow Mode?
  602.  ELSE                                       ;    No, fast mode
  603.   IF ( CPU_CLOCK_JUST ^ OSC_CR0_CPU_24MHz ) ;    As fast as 24MHz?
  604.                                             ;       no, set midpoint POR in user code, if desired
  605.   ELSE ; 24HMz                              ;
  606.     or    reg[VLT_CR],  VLT_CR_POR_HIGH     ;      yes, highest POR trip point required
  607.   ENDIF ; 24MHz
  608.  ENDIF ; Slow Mode
  609. ENDIF ; 5.0V Operation
  610.  
  611.     M8C_SetBank0
  612.  
  613.     ;----------------------------
  614.     ; Wrap up and invoke "main"
  615.     ;----------------------------
  616.  
  617.     ; Disable the Sleep interrupt that was used for timing above.  In fact,
  618.     ; no interrupts should be enabled now, so may as well clear the register.
  619.     ;
  620.     mov  reg[INT_MSK0],0
  621.  
  622.     ; Everything has started OK. Now select requested CPU & sleep frequency.
  623.     ; And put decimator in full mode so it does not consume too much current.
  624.     ;
  625.     M8C_SetBank1
  626.     mov  reg[OSC_CR0],(SELECT_32K_JUST | PLL_MODE_JUST | SLEEP_TIMER_JUST | CPU_CLOCK_JUST)
  627.     or   reg[DEC_CR2],80h                    ; Put decimator in full mode
  628.     M8C_SetBank0
  629.  
  630.     ; Global Interrupt are NOT enabled, this should be done in main().
  631.     ; LVD is set but will not occur unless Global Interrupts are enabled.
  632.     ; Global Interrupts should be enabled as soon as possible in main().
  633.     ;
  634.     mov  reg[INT_VC],0             ; Clear any pending interrupts which may
  635.                                    ; have been set during the boot process.
  636. IF      (TOOLCHAIN & HITECH)
  637.         ljmp  startup                  ; Jump to C compiler startup code
  638. ELSE
  639. IF ENABLE_LJMP_TO_MAIN
  640.     ljmp  _main                    ; goto main (no return)
  641. ELSE
  642.     lcall _main                    ; call main
  643. .Exit:
  644.     jmp  .Exit                     ; Wait here after return till power-off or reset
  645. ENDIF
  646. ENDIF ; TOOLCHAIN
  647.  
  648.     ;---------------------------------
  649.     ; Library Access to Global Parms
  650.     ;---------------------------------
  651.     ;
  652.  bGetPowerSetting:
  653. _bGetPowerSetting:
  654.     ; Returns value of POWER_SETTING in the A register.
  655.     ; No inputs. No Side Effects.
  656.     ;
  657.     mov   A, POWER_SETTING
  658.     ret
  659.  
  660. IF      (TOOLCHAIN & HITECH)
  661. ELSE
  662.     ;---------------------------------
  663.     ; Order Critical RAM & ROM AREAs
  664.     ;---------------------------------
  665.     ;  'TOP' is all that has been defined so far...
  666.  
  667.     ;  ROM AREAs for C CONST, static & global items
  668.     ;
  669.     AREA lit               (ROM, REL, CON)   ; 'const' definitions
  670.     AREA idata             (ROM, REL, CON)   ; Constants for initializing RAM
  671. __idata_start:
  672.  
  673.     AREA func_lit          (ROM, REL, CON)   ; Function Pointers
  674. __func_lit_start:
  675.  
  676. IF ( SYSTEM_LARGE_MEMORY_MODEL )
  677.     ; We use the func_lit area to store a pointer to extended initialized
  678.     ; data (xidata) area that follows the text area. Func_lit isn't
  679.     ; relocated by the code compressor, but the text area may shrink and
  680.     ; that moves xidata around.
  681.     ;
  682. __pXIData:         word __text_end           ; ptr to extended idata
  683. ENDIF
  684.  
  685.     AREA psoc_config       (ROM, REL, CON)   ; Configuration Load & Unload
  686.     AREA UserModules       (ROM, REL, CON)   ; User Module APIs
  687.  
  688.     ; CODE segment for general use
  689.     ;
  690.     AREA text (ROM, REL, CON)
  691. __text_start:
  692.  
  693.     ; RAM area usage
  694.     ;
  695.     AREA data              (RAM, REL, CON)   ; initialized RAM
  696. __data_start:
  697.  
  698.     AREA virtual_registers (RAM, REL, CON)   ; Temp vars of C compiler
  699.     AREA InterruptRAM      (RAM, REL, CON)   ; Interrupts, on Page 0
  700.     AREA bss               (RAM, REL, CON)   ; general use
  701. __bss_start:
  702.  
  703. ENDIF ; TOOLCHAIN
  704.  
  705. ; end of file boot.asm

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